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authorAlexander Shiyan <shc_work@mail.ru>2014-06-07 20:09:25 +0400
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 16:10:11 +0800
commitbb9c3398efd109e48932af46c3e1fed10adddc17 (patch)
tree3e01455de63201727c24dbddf9dddb0310fb762a
parentd7f9891500aa23bd5d29c37621be82a90c4e25d9 (diff)
downloadop-kernel-dev-bb9c3398efd109e48932af46c3e1fed10adddc17.zip
op-kernel-dev-bb9c3398efd109e48932af46c3e1fed10adddc17.tar.gz
ARM: i.MX27 clk: Separate DT and non-DT init procedure
This patch separates DT and non-DT clock initialization procedure, so we can avoid a lot of unneeded clk_register_clkdev() for DT case. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r--arch/arm/mach-imx/clk-imx27.c39
1 files changed, 24 insertions, 15 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 317a662..f5a6a3f 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -89,10 +89,9 @@ enum mx27_clks {
static struct clk *clk[clk_max];
static struct clk_onecell_data clk_data;
-int __init mx27_clocks_init(unsigned long fref)
+static void __init _mx27_clocks_init(unsigned long fref)
{
- int i;
- struct device_node *np;
+ unsigned i;
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckih] = imx_clk_fixed("ckih", fref);
@@ -206,12 +205,16 @@ int __init mx27_clocks_init(unsigned long fref)
pr_err("i.MX27 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
- np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
- if (np) {
- clk_data.clks = clk;
- clk_data.clk_num = ARRAY_SIZE(clk);
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
- }
+ clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
+
+ clk_prepare_enable(clk[emi_ahb_gate]);
+
+ imx_print_silicon_rev("i.MX27", mx27_revision());
+}
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+ _mx27_clocks_init(fref);
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
@@ -274,14 +277,9 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
- clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
- clk_prepare_enable(clk[emi_ahb_gate]);
-
- imx_print_silicon_rev("i.MX27", mx27_revision());
-
return 0;
}
@@ -298,5 +296,16 @@ int __init mx27_clocks_init_dt(void)
break;
}
- return mx27_clocks_init(fref);
+ _mx27_clocks_init(fref);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+ BUG_ON(!np);
+
+ clk_data.clks = clk;
+ clk_data.clk_num = ARRAY_SIZE(clk);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+ mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
+
+ return 0;
}
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