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| author | Arnaud Patard <arnaud.patard@rtp-net.org> | 2005-05-07 18:51:51 +0200 |
|---|---|---|
| committer | Jaroslav Kysela <perex@suse.cz> | 2005-05-29 10:06:22 +0200 |
| commit | a488e033861363f64ed90d01622e0c30b382b753 (patch) | |
| tree | b506a8963ccfd18870a46d5a685063e45a90c88c | |
| parent | 22bc30c84b4dc092deb2b14deb0603b257818e63 (diff) | |
| download | op-kernel-dev-a488e033861363f64ed90d01622e0c30b382b753.zip op-kernel-dev-a488e033861363f64ed90d01622e0c30b382b753.tar.gz | |
[ALSA] cs4281 - fix DLLRDY not seen problem
CS4281 driver
Reset the FPDN bit of the EPPMC register if needed.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Jaroslav Kysela <perex@suse.cz>
| -rw-r--r-- | sound/pci/cs4281.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c index 8b42e86..b6e1854 100644 --- a/sound/pci/cs4281.c +++ b/sound/pci/cs4281.c @@ -206,7 +206,10 @@ MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); #define BA0_PMCS 0x0344 /* Power Management Control/Status */ #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ + #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ +#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ + #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ @@ -1461,6 +1464,11 @@ static int snd_cs4281_chip_init(cs4281_t *chip) int timeout; int retry_count = 2; + /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ + tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); + if (tmp & BA0_EPPMC_FPDN) + snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); + __retry: tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); if (tmp != BA0_CFLR_DEFAULT) { |
