diff options
| author | Narendra Sankar <nsankar@broadcom.com> | 2005-08-18 22:30:35 +0200 |
|---|---|---|
| committer | Bartlomiej Zolnierkiewicz <bzolnier@elka.pw.edu.pl> | 2005-08-18 22:30:35 +0200 |
| commit | 84f57fbc724e3b56dc87c37dddac89f82cf75ef6 (patch) | |
| tree | d95ee287f89e9db0d450219e733833f95d3a2214 | |
| parent | 2f09a7f4af131bf23c013ead89373deba1c7593c (diff) | |
| download | op-kernel-dev-84f57fbc724e3b56dc87c37dddac89f82cf75ef6.zip op-kernel-dev-84f57fbc724e3b56dc87c37dddac89f82cf75ef6.tar.gz | |
[PATCH] serverworks: add support for new southbridge IDE
BCM5785 (HT1000) is a Opteron Southbridge from Serverworks/Broadcom that
incorporates a single channel ATA100 IDE controller that is functionally
identical to the Serverworks CSB6 IDE controller. This patch adds support
for the new PCI device ID and also the support for this controller.
Signed-off-by: Narendra Sankar <nsankar@broadcom.com>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@elka.pw.edu.pl>
| -rw-r--r-- | drivers/ide/pci/serverworks.c | 23 | ||||
| -rw-r--r-- | include/linux/pci_ids.h | 1 |
2 files changed, 24 insertions, 0 deletions
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c index c6f5fa4..ff2e217 100644 --- a/drivers/ide/pci/serverworks.c +++ b/drivers/ide/pci/serverworks.c @@ -21,6 +21,9 @@ * * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) * + * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE + * controller same as the CSB6. Single channel ATA100 only. + * * Documentation: * Available under NDA only. Errata info very hard to get. * @@ -71,6 +74,8 @@ static u8 svwks_ratemask (ide_drive_t *drive) if (!svwks_revision) pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision); + if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) + return 2; if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { u32 reg = 0; if (isa_dev) @@ -109,6 +114,7 @@ static u8 svwks_csb_check (struct pci_dev *dev) case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: + case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: return 1; default: break; @@ -438,6 +444,13 @@ static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const cha btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; pci_write_config_byte(dev, 0x5A, btr); } + /* Setup HT1000 SouthBridge Controller - Single Channel Only */ + else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { + pci_read_config_byte(dev, 0x5A, &btr); + btr &= ~0x40; + btr |= 0x3; + pci_write_config_byte(dev, 0x5A, btr); + } return (dev->irq) ? dev->irq : 0; } @@ -629,6 +642,15 @@ static ide_pci_device_t serverworks_chipsets[] __devinitdata = { .channels = 1, /* 2 */ .autodma = AUTODMA, .bootable = ON_BOARD, + },{ /* 4 */ + .name = "SvrWks HT1000", + .init_setup = init_setup_svwks, + .init_chipset = init_chipset_svwks, + .init_hwif = init_hwif_svwks, + .init_dma = init_dma_svwks, + .channels = 1, /* 2 */ + .autodma = AUTODMA, + .bootable = ON_BOARD, } }; @@ -653,6 +675,7 @@ static struct pci_device_id svwks_pci_tbl[] = { { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, + { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, { 0, }, }; MODULE_DEVICE_TABLE(pci, svwks_pci_tbl); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 1630368..927ed48 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1580,6 +1580,7 @@ #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB |
