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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-11-20 00:31:13 -0800
committerChris Ball <chris@printf.net>2014-01-13 12:48:24 -0500
commite3c418f1b26b59841bd074baa740a43afc15199b (patch)
tree907c9258ca082d79b696f055fdff8f948c53bd53
parent5d60e500541ed154112809627f12d86056ac5f09 (diff)
downloadop-kernel-dev-e3c418f1b26b59841bd074baa740a43afc15199b.zip
op-kernel-dev-e3c418f1b26b59841bd074baa740a43afc15199b.tar.gz
mmc: SDHI: add SoC specific workaround via HW version
One of Renesas SDHI chip needs workaround to use it, and, we can judge it based on chip version. This patch adds very quick-hack workaround method, since we still don't know how many chips need workaround in the future. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Chris Ball <cjb@laptop.org>
-rw-r--r--drivers/mmc/host/sh_mobile_sdhi.c11
-rw-r--r--include/linux/mmc/tmio.h1
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index 38553ae..2d6ce25 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -33,6 +33,8 @@
#include "tmio_mmc.h"
+#define EXT_ACC 0xe4
+
struct sh_mobile_sdhi_of_data {
unsigned long tmio_flags;
};
@@ -137,6 +139,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
int irq, ret, i = 0;
bool multiplexed_isr = true;
struct tmio_mmc_dma *dma_priv;
+ u16 ver;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
@@ -219,6 +222,14 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
goto eprobe;
/*
+ * FIXME:
+ * this Workaround can be more clever method
+ */
+ ver = sd_ctrl_read16(host, CTL_VERSION);
+ if (ver == 0xCB0D)
+ sd_ctrl_write16(host, EXT_ACC, 1);
+
+ /*
* Allow one or more specific (named) ISRs or
* one or more multiplexed (un-named) ISRs.
*/
diff --git a/include/linux/mmc/tmio.h b/include/linux/mmc/tmio.h
index a1c1f32..84d9053 100644
--- a/include/linux/mmc/tmio.h
+++ b/include/linux/mmc/tmio.h
@@ -33,6 +33,7 @@
#define CTL_SDIO_IRQ_MASK 0x38
#define CTL_DMA_ENABLE 0xd8
#define CTL_RESET_SD 0xe0
+#define CTL_VERSION 0xe2
#define CTL_SDIO_REGS 0x100
#define CTL_CLK_AND_WAIT_CTL 0x138
#define CTL_RESET_SDIO 0x1e0
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