summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorThierry Reding <treding@nvidia.com>2014-04-04 15:55:15 +0200
committerPeter De Schrijver <pdeschrijver@nvidia.com>2014-04-17 14:12:46 +0300
commit4ccc402ece35695dd2884ec0b652d52ae0230f13 (patch)
treee72273317bd892e4678ee6ccf776831e863554a1
parentc61e4e75b95bda4c6fec134aa9f08b5629b532e6 (diff)
downloadop-kernel-dev-4ccc402ece35695dd2884ec0b652d52ae0230f13.zip
op-kernel-dev-4ccc402ece35695dd2884ec0b652d52ae0230f13.tar.gz
clk: tegra: Fix enabling of PLLE
When enabling the PLLE as its final step, clk_plle_enable() would accidentally OR in the value previously written to the PLLE_SS_CTRL register. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/clk/tegra/clk-pll.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1187187..7a1b70d 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -757,7 +757,7 @@ static int clk_plle_enable(struct clk_hw *hw)
val |= PLLE_SS_DISABLE;
writel(val, pll->clk_base + PLLE_SS_CTRL);
- val |= pll_readl_base(pll);
+ val = pll_readl_base(pll);
val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
pll_writel_base(val, pll);
OpenPOWER on IntegriCloud