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authorJesse Barnes <jbarnes@virtuousgeek.org>2013-05-02 10:48:08 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-05-10 21:56:28 +0200
commit2445966ee80837116498bd83084ad6d28272320c (patch)
treebbc3feac9d574cc42d6711cfc30883f64c306b92
parent177006a10b33c9bd729cd60be0a37b41a23e4df3 (diff)
downloadop-kernel-dev-2445966ee80837116498bd83084ad6d28272320c.zip
op-kernel-dev-2445966ee80837116498bd83084ad6d28272320c.tar.gz
drm/i915: go back to switch for VLV mem freq detection v2
Both the docs and the existing code were wrong. So fix both and use a switch statement like we do elsewhere to make things simple & clear. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f4b46e..556b989 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
GEN7_RC_CTL_TO_MODE);
valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
- dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
+ switch ((val >> 6) & 3) {
+ case 0:
+ case 1:
+ dev_priv->mem_freq = 800;
+ break;
+ case 2:
+ dev_priv->mem_freq = 1066;
+ break;
+ case 3:
+ dev_priv->mem_freq = 1333;
+ break;
+ }
DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
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