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authorGabor Juhos <juhosg@openwrt.org>2014-04-16 11:34:41 +0200
committerWim Van Sebroeck <wim@iguana.be>2014-06-10 21:40:48 +0200
commit23afeb613ec0e10aecfae7838a14d485db62ac52 (patch)
treee024a06e693b7b3e6f53c6db2aab20348fc7462f
parentff4e0ae5feaffd69ecf115555c6437cf4f71f806 (diff)
downloadop-kernel-dev-23afeb613ec0e10aecfae7838a14d485db62ac52.zip
op-kernel-dev-23afeb613ec0e10aecfae7838a14d485db62ac52.tar.gz
watchdog: ath79_wdt: avoid spurious restarts on AR934x
On some AR934x based systems, where the frequency of the AHB bus is relatively high, the built-in watchdog causes a spurious restart when it gets enabled. The possible cause of these restarts is that the timeout value written into the TIMER register does not reaches the hardware in time. Add an explicit delay into the ath79_wdt_enable function to avoid the spurious restarts. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> Cc: <stable@vger.kernel.org>
-rw-r--r--drivers/watchdog/ath79_wdt.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/watchdog/ath79_wdt.c b/drivers/watchdog/ath79_wdt.c
index 399c3fd..0e67d96 100644
--- a/drivers/watchdog/ath79_wdt.c
+++ b/drivers/watchdog/ath79_wdt.c
@@ -20,6 +20,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/io.h>
@@ -90,6 +91,15 @@ static inline void ath79_wdt_keepalive(void)
static inline void ath79_wdt_enable(void)
{
ath79_wdt_keepalive();
+
+ /*
+ * Updating the TIMER register requires a few microseconds
+ * on the AR934x SoCs at least. Use a small delay to ensure
+ * that the TIMER register is updated within the hardware
+ * before enabling the watchdog.
+ */
+ udelay(2);
+
ath79_wdt_wr(WDOG_REG_CTRL, WDOG_CTRL_ACTION_FCR);
/* flush write */
ath79_wdt_rr(WDOG_REG_CTRL);
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