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authorVineet Gupta <vgupta@synopsys.com>2013-05-09 13:45:12 +0530
committerVineet Gupta <vgupta@synopsys.com>2013-05-09 13:45:12 +0530
commitc917a36f5fe551748eb37bd1efdcccc1045a02ab (patch)
tree4204be45b5ae50eb412967080121664fe0ac4256
parenteacd0e950dc2100af54f2a94ae29105bf48ab921 (diff)
downloadop-kernel-dev-c917a36f5fe551748eb37bd1efdcccc1045a02ab.zip
op-kernel-dev-c917a36f5fe551748eb37bd1efdcccc1045a02ab.tar.gz
ARC: [mm] serious bug in vaddr based icache flush
vaddr used to index the cache was clipped from the wrong end, and thus would potentially fail to flush the correct lines. The problem was dorment for so long because up until the recent optimizations it was only used for ptrace break-point only flushes. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r--arch/arc/mm/cache_arc700.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index c854cf9..d48afeb 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -421,7 +421,7 @@ static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
#if (CONFIG_ARC_MMU_VER > 2)
- vaddr &= ~ICACHE_LINE_MASK;
+ vaddr &= ICACHE_LINE_MASK;
addr = phy_start;
#else
/* bits 17:13 of vaddr go as bits 4:0 of paddr */
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