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| author | Andy Fleming <afleming@freescale.com> | 2009-02-04 16:38:05 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-04 16:38:05 -0800 |
| commit | b98ac702f49042ab0c382b839465b95a2bd0cd65 (patch) | |
| tree | 344e61f5798864cdcab11e071842578765c9ba55 | |
| parent | 1fbe49328f7442090439addddf441fb5b3186e71 (diff) | |
| download | op-kernel-dev-b98ac702f49042ab0c382b839465b95a2bd0cd65.zip op-kernel-dev-b98ac702f49042ab0c382b839465b95a2bd0cd65.tar.gz | |
gianfar: Fix potential soft reset race
SOFT_RESET must be asserted for at least 3 TX clocks in order for it to work
properly. The syncs in the gfar_write() commands have been hiding this, but
we need to guarantee it.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/gianfar.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 3f7eab4..acae2d8 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -351,6 +351,9 @@ static int gfar_probe(struct of_device *ofdev, /* Reset MAC layer */ gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); + /* We need to delay at least 3 TX clocks */ + udelay(2); + tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); gfar_write(&priv->regs->maccfg1, tempval); |
