diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2013-04-24 21:30:54 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-04-26 08:42:22 -0400 |
| commit | 00b38ab35d9bd2253a4d1e659382871d2220e095 (patch) | |
| tree | 82c3bfd588f1c59a24e9dc26abcba854d146bd2f | |
| parent | 7af1ce0e0daaf181335c8edc21e12d69ee5cd1d1 (diff) | |
| download | op-kernel-dev-00b38ab35d9bd2253a4d1e659382871d2220e095.zip op-kernel-dev-00b38ab35d9bd2253a4d1e659382871d2220e095.tar.gz | |
ssb: implement ssb spuravoid for chipid BCM43222
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/ssb/driver_chipcommon_pmu.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c index 23c5dbf..1173a09 100644 --- a/drivers/ssb/driver_chipcommon_pmu.c +++ b/drivers/ssb/driver_chipcommon_pmu.c @@ -687,8 +687,23 @@ void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; break; case 43222: - /* TODO: BCM43222 requires updating PLLs too */ - return; + if (spuravoid == 1) { + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815); + } else { + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0); + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855); + } + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD; + break; default: ssb_printk(KERN_ERR PFX "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", |
