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authorVipin Kumar <vipin.kumar@st.com>2012-03-14 11:47:11 +0530
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-03-27 00:58:43 +0100
commitb533f8d84f4f0807bf1bcf52017c6a267c8c4405 (patch)
tree16aeaba31da1e7a68e956f48e9b24b765f341a29
parentaea686b47c0cf97e0c6941799b523b6df87fc234 (diff)
downloadop-kernel-dev-b533f8d84f4f0807bf1bcf52017c6a267c8c4405.zip
op-kernel-dev-b533f8d84f4f0807bf1bcf52017c6a267c8c4405.tar.gz
mtd: nand/fsmc: Flip the bit only if the error index is < 4096
ECC can correct up to 8 bits in 512 bytes data + 13 bytes ecc. This means that the algorithm can correct a max of 8 bits in 4200 bits ie the error indices can be from 0 to 4199. Of these 0 to 4095 are for data and 4096 to 4199 for ecc. The driver flips the bit only if the index is <= 4096. This is a bug since the data bits are only from 0 to 4095. This patch modifies the check as < 4096 Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
-rw-r--r--drivers/mtd/nand/fsmc_nand.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index bd42339..6a0bca17 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -654,7 +654,7 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
change_bit(0, (unsigned long *)&err_idx[i]);
change_bit(1, (unsigned long *)&err_idx[i]);
- if (err_idx[i] <= chip->ecc.size * 8) {
+ if (err_idx[i] < chip->ecc.size * 8) {
change_bit(err_idx[i], (unsigned long *)dat);
i++;
}
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