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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-03-27 18:42:13 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-05-06 19:20:51 -0300
commitb7d41d6d580743b1fed1b9560d948c9ef58564bd (patch)
treea16260415dcd3b1cc476f84e8f283f68e321ba2d
parent6f550dc08369ee0bc6402963c377e65f0f2e3b71 (diff)
downloadop-kernel-dev-b7d41d6d580743b1fed1b9560d948c9ef58564bd.zip
op-kernel-dev-b7d41d6d580743b1fed1b9560d948c9ef58564bd.tar.gz
V4L/DVB: mx1-camera: compile fix
This fixes a regression of 7d58289 (mx1: prefix SOC specific defines with MX1_ and deprecate old names) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h8
-rw-r--r--drivers/media/video/mx1_camera.c8
2 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index 07be8ad..7c4870b 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -31,7 +31,13 @@
#define DMA_MODE_WRITE 1
#define DMA_MODE_MASK 1
-#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
+#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
+
+/* DMA Interrupt Mask Register */
+#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
+
+/* Channel Control Register */
+#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
#define IMX_DMA_MEMSIZE_32 (0 << 4)
#define IMX_DMA_MEMSIZE_8 (1 << 4)
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 3c8ebfc..34a6601 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -49,8 +49,6 @@
/*
* CSI registers
*/
-#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
-#define DMA_DIMR 0x08 /* Interrupt mask Register */
#define CSICR1 0x00 /* CSI Control Register 1 */
#define CSISR 0x08 /* CSI Status Register */
#define CSIRXR 0x10 /* CSI RxFIFO Register */
@@ -784,7 +782,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
pcdev);
imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO,
- IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0);
+ IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0);
/* burst length : 16 words = 64 bytes */
imx_dma_config_burstlen(pcdev->dma_chan, 0);
@@ -798,8 +796,8 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end -
&mx1_camera_sof_fiq_start);
- regs.ARM_r8 = DMA_BASE + DMA_DIMR;
- regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan);
+ regs.ARM_r8 = (long)MX1_DMA_DIMR;
+ regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan);
regs.ARM_r10 = (long)pcdev->base + CSICR1;
regs.ARM_fp = (long)pcdev->base + CSISR;
regs.ARM_sp = 1 << pcdev->dma_chan;
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