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authorChris Wilson <chris@chris-wilson.co.uk>2010-10-22 14:59:29 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-22 15:04:09 +0100
commit85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181 (patch)
treee0fdb8cf1c837c9f9365e385346d353ca0cc80d5
parent878a3c37d36142a192bdf5b6bfcf920832f431d7 (diff)
downloadop-kernel-dev-85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181.zip
op-kernel-dev-85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181.tar.gz
agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--drivers/char/agp/intel-gtt.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0c8ff6d..6b6760e 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1211,13 +1211,13 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
u32 pte_flags;
if (type_mask == AGP_USER_UNCACHED_MEMORY)
- pte_flags = GEN6_PTE_UNCACHED;
+ pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
- pte_flags = GEN6_PTE_LLC;
+ pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
} else { /* set 'normal'/'cached' to LLC by default */
- pte_flags = GEN6_PTE_LLC_MLC;
+ pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
if (gfdt)
pte_flags |= GEN6_PTE_GFDT;
}
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