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| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2008-04-22 17:09:49 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2008-04-24 12:00:41 +0200 |
| commit | 815c1be320fd51e5981c007f737aca410707baf8 (patch) | |
| tree | 80fce6967f5cba86f03449b5e8764542abd37899 | |
| parent | 7a22323b231fe5d47804f98f31a70eb34c6104a9 (diff) | |
| download | op-kernel-dev-815c1be320fd51e5981c007f737aca410707baf8.zip op-kernel-dev-815c1be320fd51e5981c007f737aca410707baf8.tar.gz | |
[ALSA] pxa2xx-ac97: Support PXA3xx AC97
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
| -rw-r--r-- | sound/arm/pxa2xx-ac97.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index 71fbf8d..5b3274b 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c @@ -112,6 +112,16 @@ static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigne static void pxa2xx_ac97_reset(struct snd_ac97 *ac97) { /* First, try cold reset */ +#ifdef CONFIG_PXA3xx + int timeout; + + /* Hold CLKBPB for 100us */ + GCR = 0; + GCR = GCR_CLKBPB; + udelay(100); + GCR = 0; +#endif + GCR &= GCR_COLD_RST; /* clear everything but nCRST */ GCR &= ~GCR_COLD_RST; /* then assert nCRST */ @@ -123,6 +133,14 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97) clk_disable(ac97conf_clk); GCR = GCR_COLD_RST; udelay(50); +#elif defined(CONFIG_PXA3xx) + timeout = 1000; + /* Can't use interrupts on PXA3xx */ + GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN); + + GCR = GCR_WARM_RST | GCR_COLD_RST; + while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--) + mdelay(10); #else GCR = GCR_COLD_RST; GCR |= GCR_CDONE_IE|GCR_SDONE_IE; @@ -143,6 +161,12 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97) GCR |= GCR_WARM_RST; pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); udelay(500); +#elif defined(CONFIG_PXA3xx) + timeout = 100; + /* Can't use interrupts */ + GCR |= GCR_WARM_RST; + while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--) + mdelay(1); #else GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN; wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1); |
