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authorAurelien Jarno <aurelien@aurel32.net>2008-02-22 16:14:58 +0100
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:41:43 -0500
commit28de57d1a9eb7e67badb731297197fcbef0cc19e (patch)
tree950fe43f059f03659c4fd87755a73610af5b20c4
parentfba4a1e63723b5ef16c21a90f06520ae37c5da98 (diff)
downloadop-kernel-dev-28de57d1a9eb7e67badb731297197fcbef0cc19e.zip
op-kernel-dev-28de57d1a9eb7e67badb731297197fcbef0cc19e.tar.gz
ssb: Add CHIPCO IRQ access functions
This patch adds functions to setup and read the CHIPCO IRQ. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/ssb/driver_chipcommon.c10
-rw-r--r--include/linux/ssb/ssb_driver_chipcommon.h4
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
index e586321..45b672a 100644
--- a/drivers/ssb/driver_chipcommon.c
+++ b/drivers/ssb/driver_chipcommon.c
@@ -353,6 +353,16 @@ void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
}
+void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+{
+ chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
+}
+
+u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
+{
+ return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
+}
+
u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
{
return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
index 536851b..b548a54 100644
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -390,6 +390,10 @@ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
u32 ticks);
+void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask);
+
/* Chipcommon GPIO pin access. */
u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
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