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| author | David S. Miller <davem@sunset.davemloft.net> | 2006-03-28 13:32:24 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-31 23:03:35 -0800 |
| commit | 73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8 (patch) | |
| tree | 7a9857e2ed5dee8e334efadd16c5939650f757be | |
| parent | 6f25f3986af0353b0bdc220f79b89c997d0ceda4 (diff) | |
| download | op-kernel-dev-73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8.zip op-kernel-dev-73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8.tar.gz | |
[SPARC64]: Document the instruction checks we do in do_sparc64_fault().
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | arch/sparc64/mm/fault.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c index 0db2f7d..6e002aa 100644 --- a/arch/sparc64/mm/fault.c +++ b/arch/sparc64/mm/fault.c @@ -327,8 +327,12 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs) insn = get_fault_insn(regs, 0); if (!insn) goto continue_fault; + /* All loads, stores and atomics have bits 30 and 31 both set + * in the instruction. Bit 21 is set in all stores, but we + * have to avoid prefetches which also have bit 21 set. + */ if ((insn & 0xc0200000) == 0xc0200000 && - (insn & 0x1780000) != 0x1680000) { + (insn & 0x01780000) != 0x01680000) { /* Don't bother updating thread struct value, * because update_mmu_cache only cares which tlb * the access came from. |
