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author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2014-07-09 15:40:14 +0200 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2014-07-16 12:34:22 +0000 |
commit | d7f3ec2b69f692d215deb991d109a3341b0d8da9 (patch) | |
tree | cb6cef33f5133fdd55028cf2d054e248a10d61a9 | |
parent | 9495898ffd2075d0fd42b573cb40c23eaea7b18e (diff) | |
download | op-kernel-dev-d7f3ec2b69f692d215deb991d109a3341b0d8da9.zip op-kernel-dev-d7f3ec2b69f692d215deb991d109a3341b0d8da9.tar.gz |
ARM: mvebu: add CA9 MPcore SoC Controller node
The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.
Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r-- | Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt | 14 | ||||
-rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 5 |
2 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt new file mode 100644 index 0000000..8781073 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt @@ -0,0 +1,14 @@ +Marvell Armada 38x CA9 MPcore SoC Controller +============================================ + +Required properties: + +- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". + +- reg: should be the register base and length as documented in the + datasheet for the CA9 MPcore SoC Control registers + +mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; +}; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 3de364e..b479eaa 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -286,6 +286,11 @@ reg = <0x20800 0x10>; }; + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; |