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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2015-07-16 21:08:24 +0200
committerLinus Walleij <linus.walleij@linaro.org>2015-07-27 13:53:37 +0200
commitbb379ceb8d9f3599ab9162ebf58d731350f4177a (patch)
treec78ea24e54200c84d485f5e08dca6b045abea370
parent0ba69e089827c24f5a4b21124185914f9de4f466 (diff)
downloadop-kernel-dev-bb379ceb8d9f3599ab9162ebf58d731350f4177a.zip
op-kernel-dev-bb379ceb8d9f3599ab9162ebf58d731350f4177a.tar.gz
dt-bindings: gpio: document bindings supported by gpio-mpc8xxx.c
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt22
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
new file mode 100644
index 0000000..805ddcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
@@ -0,0 +1,22 @@
+* Freescale MPC512x/MPC8xxx GPIO controller
+
+Required properties:
+- compatible : Should be "fsl,<soc>-gpio"
+ The following <soc>s are known to be supported:
+ mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq
+- reg : Address and length of the register set for the device
+- interrupts : Should be the port interrupt shared by all 32 pins.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+
+Example:
+
+gpio0: gpio@1100 {
+ compatible = "fsl,mpc5125-gpio";
+ #gpio-cells = <2>;
+ reg = <0x1100 0x080>;
+ interrupts = <78 0x8>;
+ status = "okay";
+};
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