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authorAndrew Bresticker <abrestic@chromium.org>2015-06-18 17:28:37 -0400
committerThierry Reding <treding@nvidia.com>2015-12-17 13:37:57 +0100
commitafff455cf4f2501d30446eefbfd0aecb14b8a0b8 (patch)
tree64ace5de7abeb420e49c91f7d4971b238749ba6d
parent6b301a059eb2ebed1b12a900e3b21a38e48dd410 (diff)
downloadop-kernel-dev-afff455cf4f2501d30446eefbfd0aecb14b8a0b8.zip
op-kernel-dev-afff455cf4f2501d30446eefbfd0aecb14b8a0b8.tar.gz
clk: tegra: pll: Fix issues with rates for VCO PLLs
Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/clk/tegra/clk-pll.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d00e328..731c685 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -752,6 +752,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(pll->lock, flags);
_get_pll_mnp(pll, &old_cfg);
+ if (pll->params->flags & TEGRA_PLL_VCO_OUT)
+ cfg.p = old_cfg.p;
if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
old_cfg.sdm_data != cfg.sdm_data)
@@ -812,11 +814,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
_get_pll_mnp(pll, &cfg);
- pdiv = _hw_to_p_div(hw, cfg.p);
- if (pdiv < 0) {
- WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
- __clk_get_name(hw->clk), cfg.p);
+ if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
pdiv = 1;
+ } else {
+ pdiv = _hw_to_p_div(hw, cfg.p);
+ if (pdiv < 0) {
+ WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
+ clk_hw_get_name(hw), cfg.p);
+ pdiv = 1;
+ }
}
if (pll->params->set_gain)
@@ -1103,6 +1109,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(pll->lock, flags);
_get_pll_mnp(pll, &old_cfg);
+ if (pll->params->flags & TEGRA_PLL_VCO_OUT)
+ cfg.p = old_cfg.p;
if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
ret = _program_pll(hw, &cfg, rate);
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