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author | Chen-Yu Tsai <wens@csie.org> | 2016-01-21 13:26:35 +0800 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-01-25 00:01:21 +0100 |
commit | a22f8b22a9496396d7a8512225dace208645e04c (patch) | |
tree | c9b23fc7dd559f254d0f1ed6f351d981eff8fc5d | |
parent | 3a95221352a99d2dda7fc4890f70481abef22766 (diff) | |
download | op-kernel-dev-a22f8b22a9496396d7a8512225dace208645e04c.zip op-kernel-dev-a22f8b22a9496396d7a8512225dace208645e04c.tar.gz |
ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
mmc2 and mmc3 are available on the same pins, with different mux values.
However, only mmc3 supports 8 bit DDR transfer modes.
Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
set the drive strength to 40mA, which is needed for DDR.
This pinmux setting also includes the hardware reset pin for emmc.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b6ad785..1867af2 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -709,6 +709,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc3_8bit_emmc_pins: mmc3@1 { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15", + "PC24"; + allwinner,function = "mmc3"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + gmac_pins_mii_a: gmac_mii@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", |