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authorBjorn Helgaas <bhelgaas@google.com>2017-09-01 16:35:50 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-09-01 16:35:50 -0500
commit96291d565550c1fd363e488cc17cb3189d2e4cc2 (patch)
tree5edda68ba7ef9568df9a8a843a4e5c03be656ed8
parentcacf7eaf2a36cc51c24b591d681676b6d27a7a6e (diff)
downloadop-kernel-dev-96291d565550c1fd363e488cc17cb3189d2e4cc2.zip
op-kernel-dev-96291d565550c1fd363e488cc17cb3189d2e4cc2.tar.gz
PCI: Fix typos and whitespace errors
Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--CREDITS2
-rw-r--r--Documentation/devicetree/bindings/pci/83xx-512x-pci.txt6
-rw-r--r--Documentation/devicetree/bindings/pci/altera-pcie.txt18
-rw-r--r--Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt24
-rw-r--r--Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/hisilicon-pcie.txt4
-rw-r--r--Documentation/devicetree/bindings/pci/kirin-pcie.txt8
-rw-r--r--Documentation/devicetree/bindings/pci/layerscape-pci.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/mvebu-pci.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/pci-armada8k.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/pci-keystone.txt15
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie.txt4
-rw-r--r--Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/rcar-pci.txt7
-rw-r--r--Documentation/devicetree/bindings/pci/rockchip-pcie.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt22
-rw-r--r--Documentation/devicetree/bindings/pci/spear13xx-pcie.txt6
-rw-r--r--Documentation/devicetree/bindings/pci/ti-pci.txt8
-rw-r--r--Documentation/devicetree/bindings/pci/versatile.txt2
-rw-r--r--Documentation/devicetree/bindings/pci/xgene-pci-msi.txt5
-rw-r--r--Documentation/devicetree/bindings/pci/xgene-pci.txt8
-rw-r--r--Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt7
-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/pci/dwc/Kconfig12
-rw-r--r--drivers/pci/dwc/pci-dra7xx.c1
-rw-r--r--drivers/pci/dwc/pci-keystone-dw.c2
-rw-r--r--drivers/pci/dwc/pcie-designware-ep.c2
-rw-r--r--drivers/pci/dwc/pcie-designware-host.c2
-rw-r--r--drivers/pci/dwc/pcie-designware.c2
-rw-r--r--drivers/pci/dwc/pcie-designware.h2
-rw-r--r--drivers/pci/host/pcie-rockchip.c2
-rw-r--r--drivers/pci/host/pcie-xilinx.c2
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c4
-rw-r--r--drivers/pci/quirks.c2
-rw-r--r--include/linux/aer.h5
-rw-r--r--include/linux/pcieport_if.h2
37 files changed, 99 insertions, 103 deletions
diff --git a/CREDITS b/CREDITS
index 5d09c26..0d2d60d 100644
--- a/CREDITS
+++ b/CREDITS
@@ -2090,7 +2090,7 @@ S: Kuala Lumpur, Malaysia
N: Mohit Kumar
D: ST Microelectronics SPEAr13xx PCI host bridge driver
-D: Synopsys Designware PCI host bridge driver
+D: Synopsys DesignWare PCI host bridge driver
N: Gabor Kuti
E: seasons@falcon.sch.bme.hu
diff --git a/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt b/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt
index 35a4653..b9165b7 100644
--- a/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt
+++ b/Documentation/devicetree/bindings/pci/83xx-512x-pci.txt
@@ -1,11 +1,11 @@
* Freescale 83xx and 512x PCI bridges
-Freescale 83xx and 512x SOCs include the same pci bridge core.
+Freescale 83xx and 512x SOCs include the same PCI bridge core.
83xx/512x specific notes:
- reg: should contain two address length tuples
- The first is for the internal pci bridge registers
- The second is for the pci config space access registers
+ The first is for the internal PCI bridge registers
+ The second is for the PCI config space access registers
Example (MPC8313ERDB)
pci0: pci@e0008500 {
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
index 2951a6a..4958801 100644
--- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -7,21 +7,21 @@ Required properties:
"Txs": TX slave port region
"Cra": Control register access region
- interrupt-parent: interrupt source phandle.
-- interrupts: specifies the interrupt source of the parent interrupt controller.
- The format of the interrupt specifier depends on the parent interrupt
- controller.
+- interrupts: specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends
+ on the parent interrupt controller.
- device_type: must be "pci"
- #address-cells: set to <3>
-- #size-cells: set to <2>
+- #size-cells: set to <2>
- #interrupt-cells: set to <1>
-- ranges: describes the translation of addresses for root ports and standard
- PCI regions.
+- ranges: describes the translation of addresses for root ports and
+ standard PCI regions.
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCIe interface to interrupt numbers.
Optional properties:
-- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
- controller.
+- msi-parent: Link to the hardware entity that serves as the MSI controller
+ for this PCIe controller.
- bus-range: PCI bus numbers covered
Example
@@ -45,5 +45,5 @@ Example
<0 0 0 3 &pcie_0 3>,
<0 0 0 4 &pcie_0 4>;
ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
- 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+ 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
};
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 5ecaea1..4e4aee4 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
- reg: base addresses and lengths of the PCIe controller (DBI),
- the phy controller, and configuration address space.
+ the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
- "dbi"
- "phy"
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index b2480dd..1da7ade 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -1,4 +1,4 @@
-* Synopsys Designware PCIe interface
+* Synopsys DesignWare PCIe interface
Required properties:
- compatible: should contain "snps,dw-pcie" to identify the core.
@@ -17,29 +17,27 @@ RC mode:
properties to define the mapping of the PCIe interface to interrupt
numbers.
EP mode:
-- num-ib-windows: number of inbound address translation
- windows
-- num-ob-windows: number of outbound address translation
- windows
+- num-ib-windows: number of inbound address translation windows
+- num-ob-windows: number of outbound address translation windows
Optional properties:
- num-lanes: number of lanes to use (this property should be specified unless
the link is brought already up in BIOS)
-- reset-gpio: gpio pin number of power good signal
+- reset-gpio: GPIO pin number of power good signal
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
RC mode:
-- num-viewport: number of view ports configured in
- hardware. If a platform does not specify it, the driver assumes 2.
-- bus-range: PCI bus numbers covered (it is recommended
- for new devicetrees to specify this property, to keep backwards
- compatibility a range of 0x00-0xff is assumed if not present)
+- num-viewport: number of view ports configured in hardware. If a platform
+ does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
+ to specify this property, to keep backwards compatibility a range of
+ 0x00-0xff is assumed if not present)
+
EP mode:
-- max-functions: maximum number of functions that can be
- configured
+- max-functions: maximum number of functions that can be configured
Example configuration:
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index cf92d3b..7b1e48b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -1,6 +1,6 @@
* Freescale i.MX6 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index a339dbb..b0fd3ba 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -1,7 +1,7 @@
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
-HiSilicon PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver and inherits
+HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
index 68ffa0f..6e217c6 100644
--- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -1,8 +1,8 @@
HiSilicon Kirin SoCs PCIe host DT description
-Kirin PCIe host controller is based on Designware PCI core.
-It shares common functions with PCIe Designware core driver
-and inherits common properties defined in
+Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.
Additional properties are described here:
@@ -16,7 +16,7 @@ Required properties
"apb": apb Ctrl register defined by Kirin;
"phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
-- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index ee1c72d5..e00c706 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -16,7 +16,7 @@ Required properties:
"fsl,ls1021a-pcie", "snps,dw-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
"fsl,ls1046a-pcie"
-- reg: base addresses and lengths of the PCIe controller
+- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index 2de6f65..196e034 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -77,7 +77,7 @@ and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
multiple lanes. If this property is not found, we assume that the
value is 0.
-- reset-gpios: optional gpio to PERST#
+- reset-gpios: optional GPIO to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion, if not
specified will default to 100ms, as required by the PCIe specification.
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 598533a..c54a843 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -1,6 +1,6 @@
* Marvell Armada 7K/8K PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index d08a4d5..7e05487 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -1,12 +1,12 @@
TI Keystone PCIe interface
-Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
-It shares common functions with PCIe Designware core driver and inherit
-common properties defined in
+Keystone PCI host Controller is based on the Synopsys DesignWare PCI
+hardware version 3.65. It shares common functions with the PCIe DesignWare
+core driver and inherits common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
-for the details of Designware DT bindings. Additional properties are
+for the details of DesignWare DT bindings. Additional properties are
described here as well as properties that are not applicable.
Required Properties:-
@@ -52,13 +52,12 @@ pcie_intc: Interrupt controller device node for Legacy IRQ chip
};
Optional properties:-
- phys: phandle to Generic Keystone SerDes phy for PCI
- phy-names: name of the Generic Keystine SerDes phy for PCI
+ phys: phandle to generic Keystone SerDes PHY for PCI
+ phy-names: name of the generic Keystone SerDes PHY for PCI
- If boot loader already does PCI link establishment, then phys and
phy-names shouldn't be present.
interrupts: platform interrupt for error interrupts.
-Designware DT Properties not applicable for Keystone PCI
+DesignWare DT Properties not applicable for Keystone PCI
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
-
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 9d418b7..1425bb6 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -20,7 +20,7 @@
Value type: <stringlist>
Definition: Must include the following entries
- "parf" Qualcomm specific registers
- - "dbi" Designware PCIe registers
+ - "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "config" PCIe configuration space
@@ -180,7 +180,7 @@
- <name>-gpios:
Usage: optional
Value type: <prop-encoded-array>
- Definition: List of phandle and gpio specifier pairs. Should contain
+ Definition: List of phandle and GPIO specifier pairs. Should contain
- "perst-gpios" PCIe endpoint reset signal line
- "wake-gpios" PCIe endpoint wake signal line
diff --git a/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
index 8e0a1eb..a04ab1b 100644
--- a/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
@@ -71,7 +71,7 @@
- interrupt-map: standard PCI properties to define the mapping of the
PCI interface to interrupt numbers.
- The PCI host bridge node migh have additional sub-nodes representing
+ The PCI host bridge node might have additional sub-nodes representing
the onboard PCI devices/PCI slots. Each such sub-node must have the
following mandatory properties:
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt
index bd27428..6b5b388 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
+++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
@@ -14,7 +14,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
SoC-specific version corresponding to the platform first
followed by the generic version.
-- reg: base address and length of the pcie controller registers.
+- reg: base address and length of the PCIe controller registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- bus-range: PCI bus numbers covered
@@ -25,15 +25,14 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
source for hardware related interrupts (e.g. link speed change).
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt
- numbers.
+ to define the mapping of the PCIe interface to interrupt numbers.
- clocks: from common clock binding: clock specifiers for the PCIe controller
and PCIe bus clocks.
- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie: pcie@fe000000 {
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 1453a73..1136e92 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -45,7 +45,7 @@ Required properties:
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
-- ep-gpios: contain the entry for pre-reset gpio
+- ep-gpios: contain the entry for pre-reset GPIO
- num-lanes: number of lanes to use
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 7d3b094..34a11bf 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -1,29 +1,29 @@
* Samsung Exynos 5440 PCIe interface
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the pcie controller,
- the phy controller, additional register for the phy controller.
- (Registers for the phy controller are DEPRECATED.
+- reg: base addresses and lengths of the PCIe controller,
+ the PHY controller, additional register for the PHY controller.
+ (Registers for the PHY controller are DEPRECATED.
Use the PHY framework.)
- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the confgiruation address space
+ And use the "config" instead of getting the configuration address space
from "ranges".
- NOTE: When use the "config" property, reg-names must be set.
+ NOTE: When using the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the Generic PHY.
+- phys: From PHY binding. Phandle for the generic PHY.
Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-Other common properties refer to
- Documentation/devicetree/binding/pci/designware-pcie.txt
+For other common properties, refer to
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
@@ -83,7 +83,7 @@ With using PHY framework:
...
};
-Board specific DT Entry:
+Board-specific DT Entry:
pcie@290000 {
reset-gpio = <&pin_ctrl 5 0>;
diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
index 49ea76d..d5a14f5 100644
--- a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -1,12 +1,12 @@
SPEAr13XX PCIe DT detail:
================================
-SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
+SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
controller.
Required properties:
-- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
-- phys : phandle to phy node associated with pcie controller
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- phys : phandle to PHY node associated with PCIe controller
- phy-names : must be "pcie-phy"
- All other definitions as per generic PCI bindings
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 6a07c96..7f7af30 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,6 +1,6 @@
TI PCI Controllers
-PCIe Designware Controller
+PCIe DesignWare Controller
- compatible: Should be "ti,dra7-pcie" for RC
Should be "ti,dra7-pcie-ep" for EP
- phys : list of PHY specifiers (used by generic PHY framework)
@@ -13,7 +13,7 @@ PCIe Designware Controller
HOST MODE
=========
- reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
+ - reg-names : The first entry must be "ti-conf" for the TI-specific registers
The second entry must be "rc-dbics" for the DesignWare PCIe
registers
The third entry must be "config" for the PCIe configuration space
@@ -30,7 +30,7 @@ HOST MODE
DEVICE MODE
===========
- reg : Four register ranges as listed in the reg-names property
- - reg-names : "ti-conf" for the TI specific registers
+ - reg-names : "ti-conf" for the TI-specific registers
"ep_dbics" for the standard configuration registers as
they are locally accessed within the DIF CS space
"ep_dbics2" for the standard configuration registers as
@@ -46,7 +46,7 @@ DEVICE MODE
access.
Optional Property:
- - gpios : Should be added if a gpio line is required to drive PERST# line
+ - gpios : Should be added if a GPIO line is required to drive PERST# line
NOTE: Two DT nodes may be added for each PCI controller; one for host
mode and another for device mode. So in order for PCI to
diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt
index ebd1e7d..0a702b1 100644
--- a/Documentation/devicetree/bindings/pci/versatile.txt
+++ b/Documentation/devicetree/bindings/pci/versatile.txt
@@ -5,7 +5,7 @@ PCI host controller found on the ARM Versatile PB board's FPGA.
Required properties:
- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
controller.
-- reg: base addresses and lengths of the pci controller. There must be 3
+- reg: base addresses and lengths of the PCI controller. There must be 3
entries:
- Versatile-specific registers
- Self Config space
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
index 36d881c..09ac2dc 100644
--- a/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
+++ b/Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "apm,xgene1-msi" to identify
X-Gene v1 PCIe MSI controller block.
-- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node
+- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
- reg: physical base address (0x79000000) and length (0x900000) for controller
registers. These registers include the MSI termination address and data
registers as well as the MSI interrupt status registers.
@@ -13,7 +13,8 @@ Required properties:
interrupt number 0x10 to 0x1f.
- interrupt-names: not required
-Each PCIe node needs to have property msi-parent that points to msi controller node
+Each PCIe node needs to have property msi-parent that points to an MSI
+controller node
Examples:
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt
index 1070b06..6fd2dec 100644
--- a/Documentation/devicetree/bindings/pci/xgene-pci.txt
+++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt
@@ -8,7 +8,7 @@ Required properties:
property.
- reg-names: Must include the following entries:
"csr": controller configuration registers.
- "cfg": pcie configuration space registers.
+ "cfg": PCIe configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
@@ -21,11 +21,11 @@ Required properties:
Optional properties:
- status: Either "ok" or "disabled".
-- dma-coherent: Present if dma operations are coherent
+- dma-coherent: Present if DMA operations are coherent
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie0: pcie@1f2b0000 {
status = "disabled";
@@ -51,7 +51,7 @@ SoC specific DT Entry:
};
-Board specific DT Entry:
+Board-specific DT Entry:
&pcie0 {
status = "ok";
};
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 3259798..01bf7fd 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -15,9 +15,9 @@ Required properties:
- device_type: must be "pci"
- interrupts: Should contain NWL PCIe interrupt
- interrupt-names: Must include the following entries:
- "msi1, msi0": interrupt asserted when MSI is received
+ "msi1, msi0": interrupt asserted when an MSI is received
"intx": interrupt asserted when a legacy interrupt is received
- "misc": interrupt asserted when miscellaneous is received
+ "misc": interrupt asserted when miscellaneous interrupt is received
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
mapping of the PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
@@ -26,7 +26,8 @@ Required properties:
detailed explanation
- msi-controller: indicates that this is MSI controller node
- msi-parent: MSI parent of the root complex itself
-- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts
+- legacy-interrupt-controller: Interrupt controller device node for Legacy
+ interrupts
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: should be set to 1
- #address-cells: specifies the number of cells needed to encode an
diff --git a/MAINTAINERS b/MAINTAINERS
index f66488d..4c003c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10136,7 +10136,7 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained
F: drivers/pci/dwc/pci-exynos.c
-PCI DRIVER FOR SYNOPSIS DESIGNWARE
+PCI DRIVER FOR SYNOPSYS DESIGNWARE
M: Jingoo Han <jingoohan1@gmail.com>
M: Joao Pinto <Joao.Pinto@synopsys.com>
L: linux-pci@vger.kernel.org
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index d275aad..22ec82f 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -25,7 +25,7 @@ config PCI_DRA7XX
work either as EP or RC. In order to enable host-specific features
PCI_DRA7XX_HOST must be selected and in order to enable device-
specific features PCI_DRA7XX_EP must be selected. This uses
- the Designware core.
+ the DesignWare core.
if PCI_DRA7XX
@@ -97,8 +97,8 @@ config PCI_KEYSTONE
select PCIE_DW_HOST
help
Say Y here if you want to enable PCI controller support on Keystone
- SoCs. The PCI controller on Keystone is based on Designware hardware
- and therefore the driver re-uses the Designware core functions to
+ SoCs. The PCI controller on Keystone is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
implement the driver.
config PCI_LAYERSCAPE
@@ -132,7 +132,7 @@ config PCIE_QCOM
select PCIE_DW_HOST
help
Say Y here to enable PCIe controller support on Qualcomm SoCs. The
- PCIe controller uses the Designware core plus Qualcomm-specific
+ PCIe controller uses the DesignWare core plus Qualcomm-specific
hardware wrappers.
config PCIE_ARMADA_8K
@@ -145,8 +145,8 @@ config PCIE_ARMADA_8K
help
Say Y here if you want to enable PCIe controller support on
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
- Designware hardware and therefore the driver re-uses the
- Designware core functions to implement the driver.
+ DesignWare hardware and therefore the driver re-uses the
+ DesignWare core functions to implement the driver.
config PCIE_ARTPEC6
bool "Axis ARTPEC-6 PCIe controller"
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index f2fc5f4..a6f972e 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -275,7 +275,6 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
-
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{
struct dra7xx_pcie *dra7xx = arg;
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 8bc626e..6eb21aa 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -1,5 +1,5 @@
/*
- * Designware application register space functions for Keystone PCI controller
+ * DesignWare application register space functions for Keystone PCI controller
*
* Copyright (C) 2013-2014 Texas Instruments., Ltd.
* http://www.ti.com
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 3984063..e38747c 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -1,5 +1,5 @@
/**
- * Synopsys Designware PCIe Endpoint controller driver
+ * Synopsys DesignWare PCIe Endpoint controller driver
*
* Copyright (C) 2017 Texas Instruments
* Author: Kishon Vijay Abraham I <kishon@ti.com>
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020..e71450b 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -1,5 +1,5 @@
/*
- * Synopsys Designware PCIe host controller driver
+ * Synopsys DesignWare PCIe host controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af2..daae8dd6 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -1,5 +1,5 @@
/*
- * Synopsys Designware PCIe host controller driver
+ * Synopsys DesignWare PCIe host controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b4d2a89..cca0b93 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -1,5 +1,5 @@
/*
- * Synopsys Designware PCIe host controller driver
+ * Synopsys DesignWare PCIe host controller driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 7bb9870..5fbdc38 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -6,7 +6,7 @@
* Author: Shawn Lin <shawn.lin@rock-chips.com>
* Wenrui Li <wenrui.li@rock-chips.com>
*
- * Bits taken from Synopsys Designware Host controller driver and
+ * Bits taken from Synopsys DesignWare Host controller driver and
* ARM PCI Host generic driver.
*
* This program is free software: you can redistribute it and/or modify
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f63fa5e..168db04 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -5,7 +5,7 @@
*
* Based on the Tegra PCIe driver
*
- * Bits taken from Synopsys Designware Host controller driver and
+ * Bits taken from Synopsys DesignWare Host controller driver and
* ARM PCI Host generic driver.
*
* This program is free software: you can redistribute it and/or modify
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index b1303b3..890efcc 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -5,10 +5,10 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * This file implements the core part of PCI-Express AER. When an pci-express
+ * This file implements the core part of PCIe AER. When a PCIe
* error is delivered, an error message will be collected and printed to
* console, then, an error recovery procedure will be executed by following
- * the pci error recovery rules.
+ * the PCI error recovery rules.
*
* Copyright (C) 2006 Intel Corp.
* Tom Long Nguyen (tom.l.nguyen@intel.com)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6967c6b..8ae7ee7 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2061,7 +2061,7 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
/*
* The 82575 and 82598 may experience data corruption issues when transitioning
- * out of L0S. To prevent this we need to disable L0S on the pci-e link
+ * out of L0S. To prevent this we need to disable L0S on the PCIe link.
*/
static void quirk_disable_aspm_l0s(struct pci_dev *dev)
{
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 04602cb..43799bd 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -39,7 +39,7 @@ struct aer_capability_regs {
};
#if defined(CONFIG_PCIEAER)
-/* pci-e port driver needs this function to enable aer */
+/* PCIe port driver needs this function to enable AER */
int pci_enable_pcie_error_reporting(struct pci_dev *dev);
int pci_disable_pcie_error_reporting(struct pci_dev *dev);
int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
@@ -67,7 +67,6 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
- int severity,
- struct aer_capability_regs *aer_regs);
+ int severity, struct aer_capability_regs *aer_regs);
#endif //_AER_H_
diff --git a/include/linux/pcieport_if.h b/include/linux/pcieport_if.h
index afcd130..12542f5 100644
--- a/include/linux/pcieport_if.h
+++ b/include/linux/pcieport_if.h
@@ -38,7 +38,7 @@ static inline void set_service_data(struct pcie_device *dev, void *data)
dev->priv_data = data;
}
-static inline void* get_service_data(struct pcie_device *dev)
+static inline void *get_service_data(struct pcie_device *dev)
{
return dev->priv_data;
}
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