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authorChris Rattray <crattray@opensource.wolfsonmicro.com>2013-01-18 08:43:09 +0000
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-01-18 17:46:28 +0900
commit94e205bfb73b6d19028dbd40404219fdeb27175e (patch)
tree2c6a6a0697e37d46124f0eec5d28f3a304fd8575
parentc712326d6c1e74678791d5864cd2ed283e1cc572 (diff)
downloadop-kernel-dev-94e205bfb73b6d19028dbd40404219fdeb27175e.zip
op-kernel-dev-94e205bfb73b6d19028dbd40404219fdeb27175e.tar.gz
ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock
Sets the ADSP1 clock rate to match the system clock rate. To support this the codec driver provides details of register containing the system clock control bits. Signed-off-by: Chris Rattray <crattray@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
-rw-r--r--sound/soc/codecs/wm_adsp.c33
-rw-r--r--sound/soc/codecs/wm_adsp.h3
2 files changed, 36 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index 5841285..9e31162 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -103,6 +103,13 @@
#define ADSP1_START_SHIFT 0 /* DSP1_START */
#define ADSP1_START_WIDTH 1 /* DSP1_START */
+/*
+ * ADSP1 Control 31
+ */
+#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
+
#define ADSP2_CONTROL 0
#define ADSP2_CLOCKING 1
#define ADSP2_STATUS1 4
@@ -806,12 +813,38 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
struct wm_adsp *dsp = &dsps[w->shift];
int ret;
+ int val;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
ADSP1_SYS_ENA, ADSP1_SYS_ENA);
+ /*
+ * For simplicity set the DSP clock rate to be the
+ * SYSCLK rate rather than making it configurable.
+ */
+ if(dsp->sysclk_reg) {
+ ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
+ ret);
+ return ret;
+ }
+
+ val = (val & dsp->sysclk_mask)
+ >> dsp->sysclk_shift;
+
+ ret = regmap_update_bits(dsp->regmap,
+ dsp->base + ADSP1_CONTROL_31,
+ ADSP1_CLK_SEL_MASK, val);
+ if (ret != 0) {
+ adsp_err(dsp, "Failed to set clock rate: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
ret = wm_adsp_load(dsp);
if (ret != 0)
goto err;
diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index 41206d7..cb8871a 100644
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -40,6 +40,9 @@ struct wm_adsp {
struct regmap *regmap;
int base;
+ int sysclk_reg;
+ int sysclk_mask;
+ int sysclk_shift;
struct list_head alg_regions;
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