diff options
| author | David S. Miller <davem@davemloft.net> | 2016-05-09 00:15:31 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-05-09 00:15:31 -0400 |
| commit | 908578e7d5f69087241434c872f8f4a8ab70045f (patch) | |
| tree | da7a5e9ca84fca47cd9847938cf4f7c1d385de58 | |
| parent | 59efcbaf434964f324928619fcd0a6f506134753 (diff) | |
| parent | c66b2581123cd1527b6a084f39e9271cb02673b7 (diff) | |
| download | op-kernel-dev-908578e7d5f69087241434c872f8f4a8ab70045f.zip op-kernel-dev-908578e7d5f69087241434c872f8f4a8ab70045f.tar.gz | |
Merge branch 'sh_eth-sw-reset'
Sergei Shtylyov says:
====================
sh_eth: couple of software reset bit cleanups
Here's a set of 2 patches against DaveM's 'net-next.git' repo. We can save
on the repetitive chip reset code...
[1/2] sh_eth: call sh_eth_tsu_write() from sh_eth_chip_reset_giga()
[2/2] sh_eth: reuse sh_eth_chip_reset()
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 07e2963..04cd39f 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -537,11 +537,7 @@ static struct sh_eth_cpu_data r7s72100_data = { static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) { - struct sh_eth_private *mdp = netdev_priv(ndev); - - /* reset device */ - sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); - mdelay(1); + sh_eth_chip_reset(ndev); sh_eth_select_mii(ndev); } @@ -725,8 +721,8 @@ static struct sh_eth_cpu_data sh7757_data = { #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) static void sh_eth_chip_reset_giga(struct net_device *ndev) { - int i; u32 mahr[2], malr[2]; + int i; /* save MAHR and MALR */ for (i = 0; i < 2; i++) { @@ -734,9 +730,7 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev) mahr[i] = ioread32((void *)GIGA_MAHR(i)); } - /* reset device */ - iowrite32(ARSTR_ARST, (void *)(SH_GIGA_ETH_BASE + 0x1800)); - mdelay(1); + sh_eth_chip_reset(ndev); /* restore MAHR and MALR */ for (i = 0; i < 2; i++) { |
