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authorYijing Wang <wangyijing@huawei.com>2014-11-11 15:45:31 -0700
committerBjorn Helgaas <bhelgaas@google.com>2014-11-21 09:34:23 -0700
commit8dd26dc8fecab05aa92cd7f109f691c1283c5a13 (patch)
tree973359f6203f47b4bb19f533d228bcea9e935b50
parent26914233b1cc290f7b5c0189f7d121ad345df48b (diff)
downloadop-kernel-dev-8dd26dc8fecab05aa92cd7f109f691c1283c5a13.zip
op-kernel-dev-8dd26dc8fecab05aa92cd7f109f691c1283c5a13.tar.gz
PCI: xilinx: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use xilinx_pcie_msi_chip, not xilinx_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/host/pcie-xilinx.c20
1 files changed, 5 insertions, 15 deletions
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f41bc60..eca2923 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -432,20 +432,6 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
}
-/**
- * xilinx_pcie_add_bus - Add MSI chip info to PCIe bus
- * @bus: PCIe bus
- */
-static void xilinx_pcie_add_bus(struct pci_bus *bus)
-{
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
-
- xilinx_pcie_msi_chip.dev = port->dev;
- bus->msi = &xilinx_pcie_msi_chip;
- }
-}
-
/* INTx Functions */
/**
@@ -925,10 +911,14 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
.private_data = (void **)&port,
.setup = xilinx_pcie_setup,
.map_irq = of_irq_parse_and_map_pci,
- .add_bus = xilinx_pcie_add_bus,
.scan = xilinx_pcie_scan_bus,
.ops = &xilinx_pcie_ops,
};
+
+#ifdef CONFIG_PCI_MSI
+ xilinx_pcie_msi_chip.dev = port->dev;
+ hw.msi_ctrl = &xilinx_pcie_msi_chip;
+#endif
pci_common_init_dev(dev, &hw);
return 0;
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