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authorMaxime COQUELIN <maxime.coquelin@st.com>2014-06-20 13:34:54 +0200
committerLinus Walleij <linus.walleij@linaro.org>2014-07-15 20:55:15 +0200
commit7a2deccf0ef12f7f6e33150d5875020c0c94fa94 (patch)
treeca2ff9b4bc49c91074a017b8df68ceda3856fcf8
parent1795cd9b3a91d4b5473c97f491d63892442212ab (diff)
downloadop-kernel-dev-7a2deccf0ef12f7f6e33150d5875020c0c94fa94.zip
op-kernel-dev-7a2deccf0ef12f7f6e33150d5875020c0c94fa94.tar.gz
pinctrl: st: Fix irqmux handler
st_gpio_irqmux_handler() reads the status register to find out which banks inside the controller have pending IRQs. For each banks having pending IRQs, it calls the corresponding handler. Problem is that current code restricts the number of possible banks inside the controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins inside a bank, so it shouldn't be used here. On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two last banks (PIO18 & PIO19) aren't handled. This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the controller. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: <stable@vger.kernel.org> #v3.15+ Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/pinctrl-st.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 1bd6363bc9..9f43916 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
status = readl(info->irqmux_base);
- for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
+ for_each_set_bit(n, &status, info->nbanks)
__gpio_irq_handler(&info->banks[n]);
chained_irq_exit(chip, desc);
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