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| author | Ding Tianhong <dingtianhong@huawei.com> | 2017-02-06 16:47:39 +0000 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2017-02-08 00:13:57 +0100 |
| commit | 729e55225b1f6225ee7a2a358d5141a3264627c4 (patch) | |
| tree | 10d8a96da7e1b3d6a3687314aa77c35bf27b8397 | |
| parent | fb6002a8268c493435d0e6d0d6ad17873919a7f6 (diff) | |
| download | op-kernel-dev-729e55225b1f6225ee7a2a358d5141a3264627c4.zip op-kernel-dev-729e55225b1f6225ee7a2a358d5141a3264627c4.tar.gz | |
clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum
This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward. So, describe it
in the device tree.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/arch_timer.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2..e926aea 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize |
