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authorDavid Daney <david.daney@cavium.com>2013-07-29 15:07:00 -0700
committerRalf Baechle <ralf@linux-mips.org>2013-08-26 15:31:52 +0200
commit71a8b7d86c0dbdd1a278e91afcefc9de4f819ec5 (patch)
treed7e40a8f5345cc8dca77c74f5bebfb811cfa379e
parentcad3b624853b6f34f19693b9812df0d473a6fd40 (diff)
downloadop-kernel-dev-71a8b7d86c0dbdd1a278e91afcefc9de4f819ec5.zip
op-kernel-dev-71a8b7d86c0dbdd1a278e91afcefc9de4f819ec5.tar.gz
MIPS: Add CPU identifiers for more OCTEON family members.
Needed to support new SOCs. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/cpu.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 632bbe5..c198615 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -141,6 +141,9 @@
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300
+#define PRID_IMP_CAVIUM_CNF71XX 0x9400
+#define PRID_IMP_CAVIUM_CN78XX 0x9500
+#define PRID_IMP_CAVIUM_CN70XX 0x9600
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -272,7 +275,7 @@ enum cpu_type_enum {
*/
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR, CPU_XLP,
+ CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
CPU_LAST
};
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