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authorCatalin Marinas <catalin.marinas@arm.com>2007-07-20 11:42:29 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-20 21:41:55 +0100
commit7092fc38ee770251aed361572bf6bed05fcf3ee2 (patch)
treea32e3b9b99d78476746afbf45f8abf4bfd69c4c1
parent69ebb22277a53f612ccd632ceb73ed87c9093412 (diff)
downloadop-kernel-dev-7092fc38ee770251aed361572bf6bed05fcf3ee2.zip
op-kernel-dev-7092fc38ee770251aed361572bf6bed05fcf3ee2.tar.gz
[ARM] 4498/1: ARMv7: Remove the L2 cache configuration via the aux ctrl register
The auxiliary control and the L2 auxiliary control registers are Cortex-A8 specific. They need to be removed from the generic ARMv7 support code. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--arch/arm/mm/proc-v7.S10
2 files changed, 0 insertions, 16 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d377376..7cc32b7 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN
Say Y here to use the predictable round-robin cache replacement
policy. Unless you specifically require this or are unsure, say N.
-config CPU_L2CACHE_DISABLE
- bool "Disable level 2 cache"
- depends on CPU_V7
- help
- Say Y here to disable the level 2 cache. If unsure, say N.
-
config CPU_BPREDICT_DISABLE
bool "Disable branch prediction"
depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 718f478..07b0269 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -176,16 +176,6 @@ __v7_setup:
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
-#ifndef CONFIG_CPU_L2CACHE_DISABLE
- @ L2 cache configuration in the L2 aux control register
- mrc p15, 1, r10, c9, c0, 2
- bic r10, r10, #(1 << 16) @ L2 outer cache
- mcr p15, 1, r10, c9, c0, 2
- @ L2 cache is enabled in the aux control register
- mrc p15, 0, r10, c1, c0, 1
- orr r10, r10, #2
- mcr p15, 0, r10, c1, c0, 1
-#endif
mrc p15, 0, r0, c1, c0, 0 @ read control register
ldr r10, cr1_clear @ get mask for bits to clear
bic r0, r0, r10 @ clear bits them
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