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| author | Lei YU <mine260309@gmail.com> | 2018-05-18 16:57:02 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-06-01 12:18:42 -0700 |
| commit | 67b6e5cfdb1fb2607a20e1e002719f01b025b197 (patch) | |
| tree | 5a91f034ed19fff3d8ae12959d1dfa9ee7a48730 | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
| download | op-kernel-dev-67b6e5cfdb1fb2607a20e1e002719f01b025b197.zip op-kernel-dev-67b6e5cfdb1fb2607a20e1e002719f01b025b197.tar.gz | |
clk: aspeed: Add 24MHz fixed clock
Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.
Signed-off-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/clk-aspeed.c | 9 | ||||
| -rw-r--r-- | include/dt-bindings/clock/aspeed-clock.h | 1 |
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 5eb50c3..4664088 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,7 +14,7 @@ #include <dt-bindings/clock/aspeed-clock.h> -#define ASPEED_NUM_CLKS 35 +#define ASPEED_NUM_CLKS 36 #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 @@ -474,6 +474,13 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* Fixed 24MHz clock */ + hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", + 0, 24000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; + /* * TODO: There are a number of clocks that not included in this driver * as more information is required: diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index d3558d8..ff29d8e 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -38,6 +38,7 @@ #define ASPEED_CLK_MAC 32 #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 |
