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authorVivek Gautam <vivek.gautam@codeaurora.org>2017-07-31 12:14:41 +0530
committerAndy Gross <andy.gross@linaro.org>2017-08-08 16:29:50 -0500
commit6785fa95fc3eb560cd51327128c928baf941dd98 (patch)
treee64cf5edfe0be3f8bbaeaec8d4d9d9963584c603
parent5a125b63dfe09884264a7bf52e46cc20c5bf07cc (diff)
downloadop-kernel-dev-6785fa95fc3eb560cd51327128c928baf941dd98.zip
op-kernel-dev-6785fa95fc3eb560cd51327128c928baf941dd98.tar.gz
arm64: dts: msm8996: Add device node for qcom qusb2 phy
Adding device node for QUSB2 phy and the required infrastructure to enable support for the same. This phy is used by dwc3 controller present on msm8996. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi8
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi51
2 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index d2196fc..2f5569b 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -88,6 +88,14 @@
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
+
+ phy@7411000 {
+ status = "okay";
+ };
+
+ phy@7412000 {
+ status = "okay";
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 8f08571..4b85e13 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -538,6 +538,57 @@
<960000000>,
<825000000>;
};
+
+ qfprom@74000 {
+ compatible = "qcom,qfprom";
+ reg = <0x74000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2p_hstx_trim: hstx_trim@24e {
+ reg = <0x24e 0x2>;
+ bits = <5 4>;
+ };
+
+ qusb2s_hstx_trim: hstx_trim@24f {
+ reg = <0x24f 0x1>;
+ bits = <1 4>;
+ };
+ };
+
+ hsusb_phy1: phy@7411000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7411000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2p_hstx_trim>;
+ status = "disabled";
+ };
+
+ hsusb_phy2: phy@7412000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7412000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ nvmem-cells = <&qusb2s_hstx_trim>;
+ status = "disabled";
+ };
};
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