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authorMatt Redfearn <matt.redfearn@imgtec.com>2015-08-20 11:30:32 +0100
committerLee Jones <lee.jones@linaro.org>2015-08-24 15:28:34 +0100
commit5a688c455066c21c133bc8ffa7b11f8c66b7fe0b (patch)
tree1f6702f5d988d0972381a6c2a110bcebdfb17c4e
parenta78ea195f77a8ed2c5f3108a8cdb9a26ebd474d8 (diff)
downloadop-kernel-dev-5a688c455066c21c133bc8ffa7b11f8c66b7fe0b.zip
op-kernel-dev-5a688c455066c21c133bc8ffa7b11f8c66b7fe0b.tar.gz
mfd: jz4740-adc: Init mask cache in generic IRQ chip
The mask cache must be initialised in the generic IRQ chip, otherwise enabling one channel will actually enable all channels when the empty mask cache is written. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
-rw-r--r--drivers/mfd/jz4740-adc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mfd/jz4740-adc.c b/drivers/mfd/jz4740-adc.c
index 408291c..5bb49f0 100644
--- a/drivers/mfd/jz4740-adc.c
+++ b/drivers/mfd/jz4740-adc.c
@@ -273,7 +273,8 @@ static int jz4740_adc_probe(struct platform_device *pdev)
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_ack = irq_gc_ack_set_bit;
- irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
+ irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0,
+ IRQ_NOPROBE | IRQ_LEVEL);
adc->gc = gc;
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