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authorAlex Deucher <alexander.deucher@amd.com>2016-08-22 18:03:22 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-24 16:25:04 -0400
commit4d6bdbad25e60eac1d14c039cbc32778e9dec8fe (patch)
tree0e372684b03e425482e21c37683cec871993d353
parent8dd31d74acc1371d143fd0b2795dc3d16fb47202 (diff)
downloadop-kernel-dev-4d6bdbad25e60eac1d14c039cbc32778e9dec8fe.zip
op-kernel-dev-4d6bdbad25e60eac1d14c039cbc32778e9dec8fe.tar.gz
drm/radeon: add support for UVD_NO_OP register
Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/r600d.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c1
3 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 1e8495c..2e00a52 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1490,6 +1490,7 @@
#define UVD_GPCOM_VCPU_DATA0 0xef10
#define UVD_GPCOM_VCPU_DATA1 0xef14
#define UVD_ENGINE_CNTL 0xef18
+#define UVD_NO_OP 0xeffc
#define UVD_SEMA_CNTL 0xf400
#define UVD_RB_ARB_CTRL 0xf480
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index c01a7c6..8faa4d5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -94,9 +94,10 @@
* 2.44.0 - SET_APPEND_CNT packet3 support
* 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
* 2.46.0 - Add PFP_SYNC_ME support on evergreen
+ * 2.47.0 - Add UVD_NO_OP register support
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 46
+#define KMS_DRIVER_MINOR 47
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 73dfe01..1ae1f13 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -669,6 +669,7 @@ static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
return r;
break;
case UVD_ENGINE_CNTL:
+ case UVD_NO_OP:
break;
default:
DRM_ERROR("Invalid reg 0x%X!\n",
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