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| author | Ben Skeggs <bskeggs@redhat.com> | 2016-03-11 13:09:28 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-03-14 10:13:47 +1000 |
| commit | 4a3f63f8089fcb22113e92b73d07c7d87ad03844 (patch) | |
| tree | 442b8ff4a4330937fcbcdacd425a01890db2bb0e | |
| parent | a8b005fd527076b01b6df16c49f71416649ac859 (diff) | |
| download | op-kernel-dev-4a3f63f8089fcb22113e92b73d07c7d87ad03844.zip op-kernel-dev-4a3f63f8089fcb22113e92b73d07c7d87ad03844.tar.gz | |
drm/nouveau/fifo/gk104: add vic plumbing
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvif/cla06f.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h index b5dec137..46301ec 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -12,6 +12,7 @@ struct kepler_channel_gpfifo_a_v0 { #define NVA06F_V0_ENGINE_MSPDEC 0x00000020 #define NVA06F_V0_ENGINE_MSPPP 0x00000040 #define NVA06F_V0_ENGINE_MSENC 0x00000080 +#define NVA06F_V0_ENGINE_VIC 0x00000100 #define NVA06F_V0_ENGINE_NVDEC 0x00000200 #define NVA06F_V0_ENGINE_NVENC0 0x00000400 #define NVA06F_V0_ENGINE_NVENC1 0x00000800 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 917ef0f..ed43510 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -67,6 +67,7 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) case NVKM_ENGINE_MSPDEC: return 0x0250; case NVKM_ENGINE_MSPPP : return 0x0260; case NVKM_ENGINE_MSVLD : return 0x0270; + case NVKM_ENGINE_VIC : return 0x0280; case NVKM_ENGINE_MSENC : return 0x0290; case NVKM_ENGINE_NVDEC : return 0x02100270; case NVKM_ENGINE_NVENC0: return 0x02100290; @@ -346,6 +347,7 @@ gk104_fifo_gpfifo[] = { { NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) }, { NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) }, { NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) }, + { NVA06F_V0_ENGINE_VIC , BIT_ULL(NVKM_ENGINE_VIC ) }, { NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) }, { NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) }, { NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) }, |
