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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2013-12-16 10:24:46 +0100
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2014-02-03 11:46:39 +0100
commit3f18b1bf599d3d13cd81fdf6bf869c458772adfe (patch)
tree4129c93afad2293865a0eaff0b2b0a44c96295c0
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
downloadop-kernel-dev-3f18b1bf599d3d13cd81fdf6bf869c458772adfe.zip
op-kernel-dev-3f18b1bf599d3d13cd81fdf6bf869c458772adfe.tar.gz
ARM: make isa_mode macro more robust and fix for v7-M
The definition of isa_mode hardcodes the values to shift PSR_J_BIT and PSR_T_BIT to move them to bits 1 and 0 respectively. Instead use __ffs to calculate the shift from the #define already used for masking. This is relevant on v7-M as there PSR_T_BIT is 0x01000000 instead of 0x00000020 for V7-[AR] and earlier. Because of that isa_mode produced values >= 0x80000 which are unsuitable to index into isa_modes[4] there and so made __show_regs read from undefined memory which resulted in hangs and crashes. Moreover isa_mode is wrong for v7-M even after this robustness fix as there is no J-bit in the PSR register. So hardcode isa_mode to "Thumb" for v7-M. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
-rw-r--r--arch/arm/include/asm/ptrace.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 04c99f3..627a03e 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -27,9 +27,13 @@ struct pt_regs {
#define thumb_mode(regs) (0)
#endif
+#ifndef CONFIG_CPU_V7M
#define isa_mode(regs) \
- ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
- (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
+ ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
+ (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
+#else
+#define isa_mode(regs) 1 /* Thumb */
+#endif
#define processor_mode(regs) \
((regs)->ARM_cpsr & MODE_MASK)
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