1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
/*
* QEMU MicroBlaze CPU
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#ifndef QEMU_MICROBLAZE_CPU_QOM_H
#define QEMU_MICROBLAZE_CPU_QOM_H
#include "qom/cpu.h"
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
#define MICROBLAZE_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
#define MICROBLAZE_CPU(obj) \
OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
#define MICROBLAZE_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
/**
* MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A MicroBlaze CPU model.
*/
typedef struct MicroBlazeCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} MicroBlazeCPUClass;
/**
* MicroBlazeCPU:
* @env: #CPUMBState
*
* A MicroBlaze CPU.
*/
typedef struct MicroBlazeCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
/* Microblaze Configuration Settings */
struct {
bool stackprot;
uint32_t base_vectors;
uint8_t use_fpu;
bool use_mmu;
bool dcache_writeback;
bool endi;
char *version;
uint8_t pvr;
} cfg;
CPUMBState env;
} MicroBlazeCPU;
static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
{
return container_of(env, MicroBlazeCPU, env);
}
#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
#endif
|
