1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
|
/*
* QEMU Alpha PCI support functions.
*
* Some of this isn't very Alpha specific at all.
*
* ??? Sparse memory access not implemented.
*/
#include "config.h"
#include "alpha_sys.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
{
return 0;
}
static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
{
}
const MemoryRegionOps alpha_pci_ignore_ops = {
.read = ignore_read,
.write = ignore_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 8,
},
.impl = {
.min_access_size = 1,
.max_access_size = 8,
},
};
/* PCI config space reads/writes, to byte-word addressable memory. */
static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
static void bw_conf1_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PCIBus *b = opaque;
pci_data_write(b, addr, val, size);
}
const MemoryRegionOps alpha_pci_conf1_ops = {
.read = bw_conf1_read,
.write = bw_conf1_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
.max_access_size = 4,
},
};
/* PCI/EISA Interrupt Acknowledge Cycle. */
static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
{
return pic_read_irq(isa_pic);
}
static void special_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
qemu_log("pci: special write cycle");
}
const MemoryRegionOps alpha_pci_iack_ops = {
.read = iack_read,
.write = special_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
};
|
