From 86feb1c860dc38e9c89e787c5210e8191800385e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 19 Mar 2010 12:00:26 -0700 Subject: tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs. Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tcg/mips') diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 566e352..f7ed0ba 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1298,7 +1298,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_ld16s: tcg_out_qemu_ld(s, args, 1 | 4); break; - case INDEX_op_qemu_ld32u: + case INDEX_op_qemu_ld32: tcg_out_qemu_ld(s, args, 2); break; case INDEX_op_qemu_ld64: @@ -1371,7 +1371,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_qemu_ld8s, { "L", "lZ" } }, { INDEX_op_qemu_ld16u, { "L", "lZ" } }, { INDEX_op_qemu_ld16s, { "L", "lZ" } }, - { INDEX_op_qemu_ld32u, { "L", "lZ" } }, + { INDEX_op_qemu_ld32, { "L", "lZ" } }, { INDEX_op_qemu_ld64, { "L", "L", "lZ" } }, { INDEX_op_qemu_st8, { "SZ", "SZ" } }, @@ -1383,7 +1383,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_qemu_ld8s, { "L", "lZ", "lZ" } }, { INDEX_op_qemu_ld16u, { "L", "lZ", "lZ" } }, { INDEX_op_qemu_ld16s, { "L", "lZ", "lZ" } }, - { INDEX_op_qemu_ld32u, { "L", "lZ", "lZ" } }, + { INDEX_op_qemu_ld32, { "L", "lZ", "lZ" } }, { INDEX_op_qemu_ld64, { "L", "L", "lZ", "lZ" } }, { INDEX_op_qemu_st8, { "SZ", "SZ", "SZ" } }, -- cgit v1.1