From fe0bd475aa31e60674f7f53b85dc293108026202 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 5 Dec 2012 07:15:22 +0400 Subject: target-xtensa: restrict available SRs by enabled options Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr, xsr) are associated with their corresponding SR and raise illegal opcode exception in case the register is not configured for the core. Signed-off-by: Max Filippov Signed-off-by: Blue Swirl --- target-xtensa/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target-xtensa/cpu.h') diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 068ad69..a73d32d 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -416,6 +416,7 @@ void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) +#define XTENSA_OPTION_ALL (~(uint64_t)0) static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, uint64_t opt) -- cgit v1.1