From 3580ecad0acf25a28464c145f2c74a929d0e57b1 Mon Sep 17 00:00:00 2001
From: Max Filippov <jcmvbkbc@gmail.com>
Date: Tue, 6 Sep 2011 03:55:35 +0400
Subject: target-xtensa: implement shifts (ST1 and RST1 groups)

- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
 target-xtensa/cpu.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'target-xtensa/cpu.h')

diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 8c3fe2e..f756b43 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -105,6 +105,10 @@ enum {
     FSR = 233,
 };
 
+enum {
+    SAR = 3,
+};
+
 typedef struct XtensaConfig {
     const char *name;
     uint64_t options;
-- 
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