From 67cce5617ee968946fc6402f02743fffaa4a1a02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 7 Jul 2013 01:47:51 +0200 Subject: target-xtensa: Introduce XtensaCPU subclasses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Register a CPU type per core registered. Save the XtensaConfig in XtensaCPUClass and copy it from there to CPUXtensaState, to avoid touching every env->config access for now. Prepares for storing per-class GDB register count. Acked-by: Max Filippov Signed-off-by: Andreas Färber --- target-xtensa/cpu-qom.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-xtensa/cpu-qom.h') diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h index b9896f2..1b9479e 100644 --- a/target-xtensa/cpu-qom.h +++ b/target-xtensa/cpu-qom.h @@ -45,6 +45,7 @@ * XtensaCPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @config: The CPU core configuration. * * An Xtensa CPU model. */ @@ -55,6 +56,8 @@ typedef struct XtensaCPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + + const XtensaConfig *config; } XtensaCPUClass; /** -- cgit v1.1