From 328f1f0f08f1aa303eef7493bd7c3d97a8d9636a Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Sun, 2 Nov 2014 17:31:45 +0000 Subject: target-tricore: Add instructions of RCR opcode format Add instructions of RCR opcode format. Add helper for madd32/64_ssov and madd32/64_suov. Add helper for msub32/64_ssov and msub32/64_suov. Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub. OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/tricore-opcodes.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target-tricore/tricore-opcodes.h') diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index bafc8fb..0a9122c 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -169,6 +169,7 @@ #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27) #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23) #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20) +#define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20) #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op) /* RCRR Format */ @@ -945,7 +946,7 @@ enum { OPC2_32_RCR_MSUB_64 = 0x03, OPC2_32_RCR_MSUBS_32 = 0x05, OPC2_32_RCR_MSUBS_64 = 0x07, - OPC2_32_RCR_MSUB_U_32 = 0x02, + OPC2_32_RCR_MSUB_U_64 = 0x02, OPC2_32_RCR_MSUBS_U_32 = 0x04, OPC2_32_RCR_MSUBS_U_64 = 0x06, }; -- cgit v1.1