From 5210977a8511fc0c4a8a1a68c01fa3b65e29edc0 Mon Sep 17 00:00:00 2001 From: Igor Kovalenko Date: Sun, 12 Jul 2009 12:35:31 +0400 Subject: sparc64: trap handling corrections MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl wrote: > On 7/12/09, Igor Kovalenko wrote: >> Good trap handling is required to process interrupts. >>  This patch fixes the following: >> >>  - sparc64 has no wim register >>  - sparc64 has no psret register, use IE bit of pstate >>   extract IE checking code to cpu_interrupts_enabled >>  - alternate globals are not available if cpu has GL feature >>   in this case bit AG of pstate is constant zero >>  - write to pstate must actually write pstate >>   even if cpu has GL feature >> >>  Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko --- target-sparc/helper.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target-sparc/helper.c') diff --git a/target-sparc/helper.c b/target-sparc/helper.c index d133294..5f9ad40 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -667,7 +667,9 @@ void cpu_reset(CPUSPARCState *env) tlb_flush(env, 1); env->cwp = 0; +#ifndef TARGET_SPARC64 env->wim = 1; +#endif env->regwptr = env->regbase + (env->cwp * 16); #if defined(CONFIG_USER_ONLY) #ifdef TARGET_SPARC64 @@ -677,7 +679,9 @@ void cpu_reset(CPUSPARCState *env) env->asi = 0x82; // Primary no-fault #endif #else +#if !defined(TARGET_SPARC64) env->psret = 0; +#endif env->psrs = 1; env->psrps = 1; CC_OP = CC_OP_FLAGS; -- cgit v1.1