From a2368e01c95a093d250a0e5d3cef53dddf642f1e Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 25 May 2015 01:28:56 +0200 Subject: target-sh4: optimize addc using add2 Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-sh4/translate.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'target-sh4/translate.c') diff --git a/target-sh4/translate.c b/target-sh4/translate.c index bcdf4f3..5c90fe3 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -644,15 +644,12 @@ static void _decode_opc(DisasContext * ctx) case 0x300e: /* addc Rm,Rn */ { TCGv t0, t1; - t0 = tcg_temp_new(); + t0 = tcg_const_tl(0); t1 = tcg_temp_new(); - tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); - tcg_gen_add_i32(t1, cpu_sr_t, t0); - tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), t0); - tcg_gen_setcond_i32(TCG_COND_GTU, t0, t0, t1); - tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0); + tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); + tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, + REG(B11_8), t0, t1, cpu_sr_t); tcg_temp_free(t0); - tcg_gen_mov_i32(REG(B11_8), t1); tcg_temp_free(t1); } return; -- cgit v1.1