From e527526d355570615533d38236818c759f29d889 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Wed, 15 Jan 2014 17:01:46 +0100 Subject: target-mips: add CPU definition for MIPS32R5 Add mips32r5-generic among CPU definitions for MIPS. Define ISA_MIPS32R3 and ISA_MIPS32R5. Signed-off-by: Petar Jovanovic Reviewed-by: Eric Johnson --- target-mips/mips-defs.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target-mips/mips-defs.h') diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index bf094a3..9dfa516 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -29,6 +29,8 @@ #define ISA_MIPS32R2 0x00000040 #define ISA_MIPS64 0x00000080 #define ISA_MIPS64R2 0x00000100 +#define ISA_MIPS32R3 0x00000200 +#define ISA_MIPS32R5 0x00000400 /* MIPS ASEs. */ #define ASE_MIPS16 0x00001000 @@ -64,6 +66,12 @@ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +/* MIPS Technologies "Release 3" */ +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) + +/* MIPS Technologies "Release 5" */ +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ -- cgit v1.1