From 6291ad77d7c57dfc52a6a938d1a77ec3ec3ad16c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 28 Jun 2013 14:22:32 +0100 Subject: linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: Peter Maydell Acked-by: Richard Henderson Signed-off-by: Andreas Färber --- target-microblaze/cpu.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'target-microblaze') diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 75ae5ba..6c35475 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -331,20 +331,6 @@ int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault -#if defined(CONFIG_USER_ONLY) -static inline void cpu_clone_regs(CPUMBState *env, target_ulong newsp) -{ - if (newsp) - env->regs[R_SP] = newsp; - env->regs[3] = 0; -} -#endif - -static inline void cpu_set_tls(CPUMBState *env, target_ulong newtls) -{ - env->regs[21] = newtls; -} - static inline int cpu_interrupts_enabled(CPUMBState *env) { return env->sregs[SR_MSR] & MSR_IE; -- cgit v1.1 From 6e42be7cd10260fd3a006d94f6c870692bf7a2c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 10 May 2013 16:34:06 +0200 Subject: cpu: Drop unnecessary dynamic casts in *_env_get_cpu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A transition from CPUFooState to FooCPU can be considered safe, just like FooCPU::env access in the opposite direction. The only benefit of the FOO_CPU() casts would be protection against bogus CPUFooState pointers, but then surrounding code would likely break, too. This should slightly improve interrupt etc. performance when going from CPUFooState to FooCPU. For any additional CPU() casts see 3556c233d931ad5ffa46a35cb25cfc057732ebb8 (qom: allow turning cast debugging off). Reported-by: Anthony Liguori Acked-by: Richard Henderson Signed-off-by: Andreas Färber --- target-microblaze/cpu-qom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-microblaze') diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 3e9c206..ec2b989 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -64,7 +64,7 @@ typedef struct MicroBlazeCPU { static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) { - return MICROBLAZE_CPU(container_of(env, MicroBlazeCPU, env)); + return container_of(env, MicroBlazeCPU, env); } #define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) -- cgit v1.1 From fd327f48f7e5892318b6dca2c9c6030618f65728 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 2 Jul 2013 20:03:00 +0200 Subject: target-microblaze: gen_intermediate_code_internal() should be inlined MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: qemu-stable@nongnu.org Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Andreas Färber --- target-microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-microblaze') diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 54f439f..27da4bf 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1737,7 +1737,7 @@ static void check_breakpoint(CPUMBState *env, DisasContext *dc) } /* generate intermediate code for basic block 'tb'. */ -static void +static inline void gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, int search_pc) { -- cgit v1.1 From 4a274212f03adaf8b5971cc39d460335392a97f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Fri, 21 Jun 2013 22:14:44 +0200 Subject: target-microblaze: Change gen_intermediate_code_internal() argument types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use MicroBlazeCPU and bool. Prepares for changing log_cpu_state() argument to CPUState and for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson Signed-off-by: Andreas Färber --- target-microblaze/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'target-microblaze') diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 27da4bf..b5cb141 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1738,9 +1738,10 @@ static void check_breakpoint(CPUMBState *env, DisasContext *dc) /* generate intermediate code for basic block 'tb'. */ static inline void -gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, - int search_pc) +gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, + bool search_pc) { + CPUMBState *env = &cpu->env; uint16_t *gen_opc_end; uint32_t pc_start; int j, lj; @@ -1941,12 +1942,12 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false); } void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true); } void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, -- cgit v1.1 From a0762859ae2aae2e221c59e2541f964f1350d68b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 16 Jun 2013 07:28:50 +0200 Subject: log: Change log_cpu_state[_mask]() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle (for lm32) Reviewed-by: Richard Henderson [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber --- target-microblaze/cpu.c | 2 +- target-microblaze/helper.c | 12 ++++++------ target-microblaze/translate.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'target-microblaze') diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index a0fcdf4..d93519e 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -35,7 +35,7 @@ static void mb_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 01d4bbf..c6c96d4 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%x ear=%x esr=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "bimm exception at pc=%x iflags=%x\n", env->sregs[SR_PC], env->iflags); env->regs[17] -= 4; - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { D(qemu_log("IMM_FLAG set at exception\n")); @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, sym); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); } } #endif @@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] = env->sregs[SR_PC]; env->sregs[SR_PC] = cpu->base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, env, 0); + //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; case EXCP_BREAK: @@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index b5cb141..eba255b 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1777,7 +1777,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT qemu_log("--------------\n"); - log_cpu_state(env, 0); + log_cpu_state(CPU(cpu), 0); #endif } -- cgit v1.1 From 91b1df8cf9e1ecaa8679c9ea8713d1e25c28e6c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 16 Jun 2013 07:49:48 +0200 Subject: cpu: Move reset logging to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle (for lm32) Reviewed-by: Richard Henderson Signed-off-by: Andreas Färber --- target-microblaze/cpu.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'target-microblaze') diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index d93519e..dce1c7e 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -33,11 +33,6 @@ static void mb_cpu_reset(CPUState *s) MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); CPUMBState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - mcc->parent_reset(s); memset(env, 0, offsetof(CPUMBState, breakpoints)); -- cgit v1.1