From 45664345fa3d6f2833177533c959f34867bbe573 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 17 Feb 2011 23:45:15 +0100 Subject: lm32: todo and documentation This patch adds general target documentation and a todo list. Signed-off-by: Michael Walle Signed-off-by: Edgar E. Iglesias --- target-lm32/README | 46 ++++++++++++++++++++++++++++++++++++++++++++++ target-lm32/TODO | 3 +++ 2 files changed, 49 insertions(+) create mode 100644 target-lm32/README create mode 100644 target-lm32/TODO (limited to 'target-lm32') diff --git a/target-lm32/README b/target-lm32/README new file mode 100644 index 0000000..a1c2c7e --- /dev/null +++ b/target-lm32/README @@ -0,0 +1,46 @@ +LatticeMico32 target +-------------------- + +General +------- +All opcodes including the JUART CSRs are supported. + + +JTAG UART +--------- +JTAG UART is routed to a serial console device. For the current boards it +is the second one. Ie to enable it in the qemu virtual console window use +the following command line parameters: + -serial vc -serial vc +This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) +available as virtual consoles. + + +Programmatically terminate the emulator +---------------------------------------- +Originally neither the LatticeMico32 nor its peripherals support a +mechanism to shut down the machine. Emulation aware programs can write to a +to a special register within the system control block to shut down the +virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the +first BSP which instantiate this model. A (32 bit) write to 0xfff0000 +causes a vm shutdown. + + +Special instructions +-------------------- +The translation recognizes one special instruction to halt the cpu: + and r0, r0, r0 +On real hardware this instruction is a nop. It is not used by GCC and +should (hopefully) not be used within hand-crafted assembly. +Insert this instruction in your idle loop to reduce the cpu load on the +host. + + +Ignoring the MSB of the address bus +----------------------------------- +Some SoC ignores the MSB on the address bus. Thus creating a shadow memory +area. As a general rule, 0x00000000-0x7fffffff is cached, whereas +0x80000000-0xffffffff is not cached and used to access IO devices. This +behaviour can be enabled with: + cpu_lm32_set_phys_msb_ignore(env, 1); + diff --git a/target-lm32/TODO b/target-lm32/TODO new file mode 100644 index 0000000..b9ea0c8 --- /dev/null +++ b/target-lm32/TODO @@ -0,0 +1,3 @@ +* disassembler (lm32-dis.c) +* linux-user emulation +* native bp/wp emulation (?) -- cgit v1.1