From fbc2ed9518efcdcdcbf0adb9539c17a65addd20a Mon Sep 17 00:00:00 2001 From: Luiz Capitulino Date: Tue, 28 May 2013 14:19:22 -0400 Subject: target-i386: fix abort on bad PML4E/PDPTE/PDE/PTE addresses The code used to walk IA-32e page-tables, and possibly PAE page-tables, uses the bit mask ~0xfff to get the next PML4E/PDPTE/PDE/PTE address. However, as we use a uint64_t to store the resulting address, that mask gets expanded to 0xfffffffffffff000 which not only ends up selecting reserved bits but also selects the XD bit (execute-disable) which happens to be enabled by Windows 8, causing qemu_get_ram_ptr() to abort. This commit fixes that problem by replacing ~0xfff by a correct mask that only selects the address bit range (ie. bits 51:12). Signed-off-by: Luiz Capitulino Reviewed-by: Laszlo Ersek --- target-i386/arch_memory_mapping.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'target-i386/arch_memory_mapping.c') diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c index 844893f..24884bd 100644 --- a/target-i386/arch_memory_mapping.c +++ b/target-i386/arch_memory_mapping.c @@ -75,6 +75,8 @@ static void walk_pte2(MemoryMappingList *list, } /* PAE Paging or IA-32e Paging */ +#define PLM4_ADDR_MASK 0xffffffffff000 /* selects bits 51:12 */ + static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr, int32_t a20_mask, target_ulong start_line_addr) { @@ -105,7 +107,7 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr, continue; } - pte_start_addr = (pde & ~0xfff) & a20_mask; + pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask; walk_pte(list, pte_start_addr, a20_mask, line_addr); } } @@ -208,7 +210,7 @@ static void walk_pdpe(MemoryMappingList *list, continue; } - pde_start_addr = (pdpe & ~0xfff) & a20_mask; + pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask; walk_pde(list, pde_start_addr, a20_mask, line_addr); } } @@ -231,7 +233,7 @@ static void walk_pml4e(MemoryMappingList *list, } line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48); - pdpe_start_addr = (pml4e & ~0xfff) & a20_mask; + pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask; walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr); } } @@ -249,7 +251,7 @@ int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env) if (env->hflags & HF_LMA_MASK) { hwaddr pml4e_addr; - pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask; + pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask; walk_pml4e(list, pml4e_addr, env->a20_mask); } else #endif -- cgit v1.1 From bff63471ced94e3a6de76b1a7375a875178d6cdc Mon Sep 17 00:00:00 2001 From: Qiao Nuohan Date: Thu, 30 May 2013 17:07:54 +0200 Subject: target-i386: Fix mask of pte index in memory mapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function walk_pte() needs pte index to calculate virtual address. However, pte index of PAE paging or IA-32e paging is 9 bit, so the mask should be 0x1ff. Signed-off-by: Qiao Nuohan Reviewed-by: Jesse Larrew Signed-off-by: Andreas Färber Signed-off-by: Luiz Capitulino --- target-i386/arch_memory_mapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-i386/arch_memory_mapping.c') diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c index 24884bd..5096fbd 100644 --- a/target-i386/arch_memory_mapping.c +++ b/target-i386/arch_memory_mapping.c @@ -38,7 +38,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr, continue; } - start_vaddr = start_line_addr | ((i & 0x1fff) << 12); + start_vaddr = start_line_addr | ((i & 0x1ff) << 12); memory_mapping_list_add_merge_sorted(list, start_paddr, start_vaddr, 1 << 12); } -- cgit v1.1