From cf1d97f07480b6197aebc489938b4e1fed78d3e7 Mon Sep 17 00:00:00 2001 From: edgar_igl Date: Tue, 13 May 2008 10:59:14 +0000 Subject: CRIS: Improve TLB management and handle delayslots at page boundaries. * Dont flush the entire qemu tlb when the $pid changes. Instead we go through the guests TLB and choose entries that need to be flushed. * Add env->dslot and handle delayslots at pageboundaries. * Remove some unused code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-cris/cpu.h | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'target-cris/cpu.h') diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 845926d..a26dd80 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -107,11 +107,10 @@ typedef struct CPUCRISState { /* Pseudo register for the kernel stack. */ uint32_t ksp; - /* These are setup up by the guest code just before transfering the - control back to the host. */ - int jmp; - uint32_t btarget; + /* Branch. */ + int dslot; int btaken; + uint32_t btarget; /* Condition flag tracking. */ uint32_t cc_op; @@ -119,10 +118,8 @@ typedef struct CPUCRISState { uint32_t cc_dest; uint32_t cc_src; uint32_t cc_result; - /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ int cc_size; - /* Extended arithmetics. */ int cc_x_live; int cc_x; @@ -137,13 +134,6 @@ typedef struct CPUCRISState { uint32_t debug2; uint32_t debug3; - struct - { - int exec_insns; - int exec_loads; - int exec_stores; - } stats; - /* FIXME: add a check in the translator to avoid writing to support register sets beyond the 4th. The ISA allows up to 256! but in practice there is no core that implements more than 4. -- cgit v1.1