From b41f7df0189dbda34be3944a48db3b98348e4bc6 Mon Sep 17 00:00:00 2001 From: edgar_igl Date: Fri, 2 May 2008 22:16:17 +0000 Subject: CRIS updates: * Support both the I and D MMUs and improve the accuracy of the MMU model. * Handle the automatic user/kernel stack pointer switching when leaving or entering user mode. * Move the CCS evaluation into helper funcs. * Make sure user-mode cannot change flags only writeable in kernel mode. * More conversion of the translator into TCG. * Handle exceptions while in a delayslot. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4299 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-cris/cpu.h | 117 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 66 insertions(+), 51 deletions(-) (limited to 'target-cris/cpu.h') diff --git a/target-cris/cpu.h b/target-cris/cpu.h index ac042d5..b62c537 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -38,6 +38,28 @@ #define EXCP_MMU_FAULT 4 #define EXCP_BREAK 16 /* trap. */ +/* Register aliases. R0 - R15 */ +#define R_FP 8 +#define R_SP 14 +#define R_ACR 15 + +/* Support regs, P0 - P15 */ +#define PR_BZ 0 +#define PR_VR 1 +#define PR_PID 2 +#define PR_SRS 3 +#define PR_WZ 4 +#define PR_EXS 5 +#define PR_EDA 6 +#define PR_MOF 7 +#define PR_DZ 8 +#define PR_EBP 9 +#define PR_ERP 10 +#define PR_SRP 11 +#define PR_CCS 13 +#define PR_USP 14 +#define PR_SPC 15 + /* CPU flags. */ #define S_FLAG 0x200 #define R_FLAG 0x100 @@ -77,27 +99,16 @@ #define NB_MMU_MODES 2 typedef struct CPUCRISState { - uint32_t debug1; - uint32_t debug2; - uint32_t debug3; - - /* - * We just store the stores to the tlbset here for later evaluation - * when the hw needs access to them. - * - * One for I and another for D. - */ - struct - { - uint32_t hi; - uint32_t lo; - } tlbsets[2][4][16]; - - uint32_t sregs[256][16]; /* grrr why so many?? */ uint32_t regs[16]; + /* P0 - P15 are referred to as special registers in the docs. */ uint32_t pregs[16]; + + /* Pseudo register for the PC. Not directly accessable on CRIS. */ uint32_t pc; + /* Pseudo register for the kernel stack. */ + uint32_t ksp; + /* These are setup up by the guest code just before transfering the control back to the host. */ int jmp; @@ -114,20 +125,19 @@ typedef struct CPUCRISState { /* size of the operation, 1 = byte, 2 = word, 4 = dword. */ int cc_size; - /* extended arithmetics. */ + /* Extended arithmetics. */ int cc_x_live; int cc_x; - int features; - int exception_index; int interrupt_request; int interrupt_vector; int fault_vector; int trap_vector; - int user_mode_only; - int halted; + uint32_t debug1; + uint32_t debug2; + uint32_t debug3; struct { @@ -136,6 +146,31 @@ typedef struct CPUCRISState { int exec_stores; } stats; + /* FIXME: add a check in the translator to avoid writing to support + register sets beyond the 4th. The ISA allows up to 256! but in + practice there is no core that implements more than 4. + + Support function registers are used to control units close to the + core. Accesses do not pass down the normal hierarchy. + */ + uint32_t sregs[4][16]; + + /* + * We just store the stores to the tlbset here for later evaluation + * when the hw needs access to them. + * + * One for I and another for D. + */ + struct + { + uint32_t hi; + uint32_t lo; + } tlbsets[2][4][16]; + + int features; + int user_mode_only; + int halted; + jmp_buf jmp_env; CPU_COMMON } CPUCRISState; @@ -225,40 +260,20 @@ void register_cris_insns (CPUCRISState *env); #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ static inline int cpu_mmu_index (CPUState *env) { - return 0; + return !!(env->pregs[PR_CCS] & U_FLAG); } -#include "cpu-all.h" - -/* Register aliases. R0 - R15 */ -#define R_FP 8 -#define R_SP 14 -#define R_ACR 15 - -/* Support regs, P0 - P15 */ -#define PR_BZ 0 -#define PR_VR 1 -#define PR_PID 2 -#define PR_SRS 3 -#define PR_WZ 4 -#define PR_MOF 7 -#define PR_DZ 8 -#define PR_EBP 9 -#define PR_ERP 10 -#define PR_SRP 11 -#define PR_CCS 13 - /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 -#define SFR_RW_MM_CFG 2][0 -#define SFR_RW_MM_KBASE_LO 2][1 -#define SFR_RW_MM_KBASE_HI 2][2 -#define SFR_R_MM_CAUSE 2][3 -#define SFR_RW_MM_TLB_SEL 2][4 -#define SFR_RW_MM_TLB_LO 2][5 -#define SFR_RW_MM_TLB_HI 2][6 +#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 +#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1 +#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2 +#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3 +#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4 +#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 +#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 +#include "cpu-all.h" #endif -- cgit v1.1