From a1ba125c0ca64b604484ddc104e533546d92088a Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Tue, 27 May 2014 17:09:55 +0100 Subject: target-arm: A64: Register VBAR_EL3 Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias Message-id: 1400980132-25949-24-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/cpu.h | 2 +- target-arm/helper.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'target-arm') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3ccbd95..8d04385 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -198,7 +198,7 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t vbar_el[3]; /* vector base address register */ + uint64_t vbar_el[4]; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index c769ef2..6a01c6a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2138,6 +2138,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, + .access = PL3_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), + .resetvalue = 0 }, REGINFO_SENTINEL }; -- cgit v1.1